9 Scripting (Perl Jobs

Deploy and manage Murex Software needed for Murex client s projects using Murex tools and scripts. Environment deployment and Management Operations Perform basic smoke tests before delivering the needed products. Act as a first level support for already deployed Murex products, re-directing, and following the issues with the corresponding support teams Act as first-level support for already deployed Murex products, re-directing, and following the issues with the corresponding support teams Configuration Management: Use Murex configuration management tools to import/export configuration items and analyse related issues Apply the configuration management methodologies. Perform database sanitization and purging procedures. Must Have Scripting (perl, awk), SQL, Unix XML, RDMS Operation. Involved in project deliverables related to his domain of expertise. Handles project deliverable end-to-end. Sets the required organization that ensures it s done according to the specifications agreed with the SL and completed timely. Business requirements analysis & Specifications writing Configuration, testing and validation. User assistance Understanding of Financial market

What Youll Need: BS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience, Hands-on experience with synthesis and place and route (P&R) tools, Proficiency with EDA tools such as DC, ICC2, and Fusion Compiler, Knowledge of advanced placement and routing rules, Experience with scripting languages like Perl and Tcl, Strong understanding of ASIC design flow, VLSI, and CAD development, Never give-up attitude and flexibility in supporting worldwide engagements, Who You Are: Excellent communicator with strong command of English, Highly motivated and self-driven, Detail-oriented with a focus on quality and performance, A team player who thrives in collaborative environments, Adaptable and eager to learn new technologies and methodologies,

What Youll Need: BS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience, Hands-on experience with synthesis and place and route (P&R) tools, Proficiency with EDA tools such as DC, ICC2, and Fusion Compiler, Knowledge of advanced placement and routing rules, Experience with scripting languages like Perl and Tcl, Strong understanding of ASIC design flow, VLSI, and CAD development, Never give-up attitude and flexibility in supporting worldwide engagements, Who You Are: Excellent communicator with strong command of English, Highly motivated and self-driven, Detail-oriented with a focus on quality and performance, A team player who thrives in collaborative environments, Adaptable and eager to learn new technologies and methodologies,

You are a seasoned professional with a strong background in Static Timing Analysis (STA) and Synopsys Design Constraints (SDC) Your expertise in RTL and System Verilog, along with your proficiency in scripting languages like Perl, Tcl, or Python, makes you stand out You have a deep understanding of front-end EDA design methodologies and experience with logic synthesis tools Your prior experience with SDC tools and RTL simulation is a significant plus You are an excellent communicator, capable of producing detailed product requirement documents, and you have a knack for translating customer needs into actionable insights for our R&D team With a BS in Electrical or Computer Engineering and over 10 years of experience in STA/Synthesis/Front-End Flows, you are ready to take on a leadership role and drive innovation at Synopsys, What Youll Be Doing: Collaborating with customers to ensure our SDC Constraints solution meets their expectations, Developing and integrating design methodologies with other Synopsys products, Tracking customer engagements and communicating status with Marketing and Upper Management, Preparing and delivering technical presentations to customers and Field Application Engineers (FAEs), Creating customer training material related to our SDC Constraints solution, Routinely meeting with customers to understand their key priorities and communicating these internally, Providing technical direction to our R&D team and championing key customer requests, The Impact You Will Have: Enhancing customer satisfaction by ensuring our solutions meet their needs and expectations, Driving the integration of our SDC Constraints solution with other Synopsys products, enhancing overall product offerings, Improving communication and collaboration between customers, marketing, and upper management, Empowering customers and FAEs with comprehensive technical knowledge through effective presentations and training materials, Influencing product development by providing valuable insights and priorities from customer feedback, Ensuring the continuous improvement and innovation of our SDC Constraints solution, What Youll Need: Proficiency with STA, SDC, Proficiency with RTL, System Verilog, Strong understanding of front-end EDA design methodologies, Strong Perl, Tcl, or Python scripting skills, Prior experience with logic synthesis tools, Prior experience using or supporting SDC tools (a significant plus), Prior experience with RTL simulation and SVA (a plus), Sound communication skills, both verbal and written, Ability to produce detailed product requirement documents, BS in Electrical or Computer Engineering with 10+ years of experience in STA/Synthesis/Front-End Flows, Who You Are: You are a highly skilled and experienced engineer with a passion for technology and innovation You possess excellent problem-solving abilities and have a customer-centric mindset You are a great communicator and collaborator, capable of working effectively with cross-functional teams

What You ll Be Doing: Execute and lead product validation of Synopsyss Formality tool by understanding requirements specifications, functional specifications, and customer use cases Lead a team of 5 or more product validation engineers Collaborate with cross-functional teams such as R&D, Product Engineering to develop, implement, and execute comprehensive validation plans based on our technical roadmap and specifications Define and manage scope, schedule, and risks associated with the validation objectives Perform in-depth customer incoming root cause analysis to understand the product weak areas and hot spots and execute proactive testing to improving product quality Use product expertise to provide technical recommendations, identify, diagnose and troubleshoot issues, and propose solutions to ensure quality and readiness of the product/solution for customer deployment Analyze product validation data to identify trends, discrepancies, and areas for improvement Prepare detailed validation reports for presenting to multi-functional teams and management The Impact You Will Have: Ensuring the quality and reliability of Synopsyss Formality product to keep standing out as a leading LEC solution in the industry Enabling timely and successful deployment of high-performance designs for our customers Contributing to the innovation and advancement of LEC and product validation technologies Strengthening collaboration and communication across R&D, Product Engineering, and Field teams What You ll Need: B.Tech or equivalent and a minimum of 8 yearsof related experience or M.Tech or equivalent and a minimum of 6 years of related experience Self-motivated individual with deep domain knowledge in Logic Equivalence Checking (LEC) including expertise in debugging and resolving LEC failures using Synopsys s Formality tool Experience and sound knowledge in design implementation including datapath optimization, CTS, UPF and DFT instrumentation Sound knowledge in HDL including SystemVerilog and VHDL Exceptional debugging skills Proficiency in software and scripting skills (Perl, Tcl, Python) Experience in cross-functional teamwork, driving projects and mentoring Who You Are: Details oriented with a focus on maintaining high standards of product quality Excellent communication, organizational, risk assessment/mitigation, and time management skills Ability to abstract up and communicate meaningful conclusions and define next steps Excellent communication and leadership skills

You Are: You are a skilled Emulation R&D Engineer with over 8 years of experience and a strong academic background in Electronic & Communication or Computer Science Engineering. Your expertise in C/C++, OOPS, and HDL languages like System Verilog and Verilog, along with your scripting skills in Perl or TCL, make you a valuable team member. You possess knowledge of protocols such as ENET, HDMI, MIPI, AMBA, and UART, and have experience with UVM and Functional Verification. You are a resourceful problem-solver, a team player, and have excellent communication skills. What You ll Be Doing: Designing and developing emulation models. Implementing and verifying digital designs using System Verilog and Verilog. Developing scripts in Perl, TCL, or other languages. Collaborating with cross-functional teams. Conducting protocol verification for various standards. Utilizing UVM for design validation. The Impact You Will Have: Enhancing emulation model efficiency. Contributing to high-performance silicon chips. Improving design reliability through verification. Streamlining workflows with automation. Ensuring protocol compliance. Driving technological advancements. What You ll Need: B.E / M.E. in Electronic & Communication / Computer Science Engineering. Proficiency in C/C++ and OOPS. Knowledge of digital design and HDL languages. Experience with scripting languages. Familiarity with multiple protocols likeethernet, pcie, cxl, CSI, DSI, UFS AMBA, CHIand UVM. Who You Are: Effective communicator. Team player. Resourceful and detail-oriented. Innovative problem-solver. Adaptable learner.

You Are: You are a skilled Emulation R&D Engineer with over 8 years of experience and a strong academic background in Electronic & Communication or Computer Science Engineering. Your expertise in C/C++, OOPS, and HDL languages like System Verilog and Verilog, along with your scripting skills in Perl or TCL, make you a valuable team member. You possess knowledge of protocols such as ENET, HDMI, MIPI, AMBA, and UART, and have experience with UVM and Functional Verification. You are a resourceful problem-solver, a team player, and have excellent communication skills. What You ll Be Doing: Designing and developing emulation models. Implementing and verifying digital designs using System Verilog and Verilog. Developing scripts in Perl, TCL, or other languages. Collaborating with cross-functional teams. Conducting protocol verification for various standards. Utilizing UVM for design validation. The Impact You Will Have: Enhancing emulation model efficiency. Contributing to high-performance silicon chips. Improving design reliability through verification. Streamlining workflows with automation. Ensuring protocol compliance. Driving technological advancements. What You ll Need: B.E / M.E. in Electronic & Communication / Computer Science Engineering. Proficiency in C/C++ and OOPS. Knowledge of digital design and HDL languages. Experience with scripting languages. Familiarity with multiple protocols likeethernet, pcie, cxl, CSI, DSI, UFS AMBA, CHIand UVM. Who You Are: Effective communicator. Team player. Resourceful and detail-oriented. Innovative problem-solver. Adaptable learner.

You Are: You are a skilled Emulation R&D Engineer with over 8 years of experience and a strong academic background in Electronic & Communication or Computer Science Engineering. Your expertise in C/C++, OOPS, and HDL languages like System Verilog and Verilog, along with your scripting skills in Perl or TCL, make you a valuable team member. You possess knowledge of protocols such as ENET, HDMI, MIPI, AMBA, and UART, and have experience with UVM and Functional Verification. You are a resourceful problem-solver, a team player, and have excellent communication skills. What You ll Be Doing: Designing and developing emulation models. Implementing and verifying digital designs using System Verilog and Verilog. Developing scripts in Perl, TCL, or other languages. Collaborating with cross-functional teams. Conducting protocol verification for various standards. Utilizing UVM for design validation. The Impact You Will Have: Enhancing emulation model efficiency. Contributing to high-performance silicon chips. Improving design reliability through verification. Streamlining workflows with automation. Ensuring protocol compliance. Driving technological advancements. What You ll Need: B.E / M.E. in Electronic & Communication / Computer Science Engineering. Proficiency in C/C++ and OOPS. Knowledge of digital design and HDL languages. Experience with scripting languages. Familiarity with multiple protocols likeethernet, pcie, cxl, CSI, DSI, UFS AMBA, CHIand UVM. Who You Are: Effective communicator. Team player. Resourceful and detail-oriented. Innovative problem-solver. Adaptable learner.

What You ll Be Doing: Implementing state-of-the-art Verification environments for the DesignWare family of synthesizable cores. Performing Verification tasks for IP cores, focusing on domains such as USB, PCI Express, Ethernet, and AMBA. Collaborating closely with the RTL design team and other expert Verification Engineers globally. Engaging in Test planning, Test environment coding at both unit and system levels, Test case coding, and debugging. Coding and analyzing functional coverage and meeting quality metric goals. Managing regression processes to ensure comprehensive verification. The Impact You Will Have: Enhancing the robustness and reliability of our IP cores, ensuring high-quality deliverables. Contributing to the development of innovative solutions that drive the Era of Smart Everything. Reducing the time-to-market for our customers by ensuring their products meet performance, power, and size requirements. Supporting the integration of more capabilities into SoCs, enabling differentiated products. Participating in a global team effort to advance cutting-edge technologies in chip design and software security. Ensuring the successful verification of complex IP cores, contributing to the overall success and reputation of Synopsys. What You ll Need: BS/BE in Electrical Engineering with 5+ years of relevant experience or MS with 3+ years of relevant experience in IP core and/or SOC verification. Proficiency in developing HVL-based test environments and implementing test plans. Hands-on experience with industry-standard simulators such as VCS, NC, and MTI, and relevant debugging tools. Strong understanding of verification methodologies like UVM/VMM/OVM. Familiarity with Verilog and scripting languages such as Perl. Basic understanding of functional and code coverage. Excellent written and oral communication skills, along with strong analytical, debugging, and problem-solving abilities. Who You Are: A self-driven individual with a passion for technology and innovation. A collaborative team player with the ability to work effectively in a global team environment. A detail-oriented professional with a commitment to delivering high-quality work. A proactive learner who stays updated with the latest industry trends and technologies.