Senior Principal Digital Design Engineer onsemi

10.0 - 14.0 years

0 Lacs

karnataka

On-site

You will be responsible for joining OnSemi's growing team in Bengaluru, India as a Sr. Principal Digital Design Engineer focused on New Product Development in Power Management. Your primary responsibilities will include working on the development of various Power Management products for consumer, industrial, and automotive applications such as DC-DC PMIC/POL, multiphase controllers, drivers, converters, LED drivers, SiC drivers, switches, and efuses. Your key responsibilities will involve collaborating with different product lines for RTL implementation of power convertor controller designs, working on digital design architecture, RTL, low power design, synthesis, and timing analysis. You will also interface with the Physical Design team for the power management chips using state-of-the-art RTL2GDS flows. As part of a large engineering team, you will collaborate effectively with design architects, digital verification, project management, and digital and analog design teams across various global locations. You will be involved in micro-architecture to RTL implementation, supporting system-level bring-up on pre-silicon platforms, and owning the technical outcome of Power Management ICs. Furthermore, you will be responsible for understanding project goals, executing with realistic schedules, reporting progress status, and supporting post-silicon validation activities. You will also lead and support customer issues, production issues, FW and system development, and failure analysis. Onsemi is a company driving disruptive innovations to create a better future, focusing on automotive and industrial end-markets. With a highly differentiated product portfolio, Onsemi aims to solve complex challenges and lead the way in creating a safer, cleaner, and smarter world. To qualify for this role, you should have a BS in Electrical Engineering or related field with 12 years of experience, or an MS with 10 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. The ideal candidate will possess a thorough understanding of the end-to-end digital design flow, RTL design, CDC, ASIC synthesis, timing analysis, P&R, UPF, system Verilog, Verilog, TCL, and Perl/Python/XML programming languages.,

Posted 3 days ago

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RTL Designer Aarna Hr Solutions

3.0 - 6.0 years

3 - 6 Lacs

Bengaluru, Karnataka, India

On-site

We are looking for talented RTL Designers to join our SoC Digital Design Team. This role involves contributing to the development of high-performance SoCs for the mobile space. The ideal candidate will have strong expertise in RTL-based digital design, excellent communication skills, and the ability to collaborate effectively with diverse global teams involved in the ASIC design lifecycle. You'll get the opportunity to work on cutting-edge SoCs that are shaping the future of mobile technology. Responsibilities: Develop micro-architecture and RTL implementation for System-on-Chips (SoCs). Take responsibility for block-level or full-chip integration and design . Be hands-on with Lint, CDC (Clock Domain Crossing), and LEC (Logic Equivalence Checking) tools, with a preference for experience in Low Power check tools . Possess a good understanding of design implementation flows and tools such as Synthesis, STA (Static Timing Analysis), and DFT (Design For Testability) . Have a good understanding and hands-on experience with database management flows , preferably ClearCase/ClearQuest . Collaborate with the functional verification team to review test plans and coverage . Experience with AXI/AHB protocols is essential. Knowledge of Networks on Chip Fabric and I/O protocols like SDCC/DDR/USB/UART/SPI would be a significant plus. Work seamlessly with global teams including ASIC design, IP, architecture, implementation, DFT, power, STA, PD, software, firmware, and validation teams. Required Skills and Qualifications: Excellent inter-personal and communication skills. Strong knowledge of digital design principles. Proficiency in RTL implementation. Familiarity with design verification processes.

Posted 1 week ago

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