RTL DESIGN LEAD ENGINEER

The ideal candidate for the RTL Design Lead Engineer position will work on IP development and integration into SoCs across various markets and technology nodes. You will be responsible for RTL design, front-end tools flow, and SoC integration/porting tasks. With over 8 years of experience, you should have a strong engineering background with exposure to front-end ASIC tool flows. You must be self-driven and able to work independently to track and complete tasks efficiently. Your expertise should include in-depth knowledge of AHB and bus infrastructures like matrix and fabrics, as well as a good understanding of ARM-based SoC architecture. Experience in ARM Cortex A/M integration or support, SoC DV methodology, and Low-Power design methodology is highly desirable. You should have hands-on experience with ASIC tools such as Lint, CDC, and possess expertise in System Verilog/Verilog RTL coding, including power-aware RTL coding and design knowledge. An understanding of Clock-Structures/Scheme and excellent communication skills are also important for this role. This position falls under the job category of VLSI (Silicon engineering) and is available in multiple locations including India (Bangalore, Hyderabad, Noida), Malaysia, Singapore, Sweden (Stockholm), and the USA (Texas).,