5 Randomization Jobs

Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices, Job Description In your new role you will: Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices, Responsible for: Designing self-checking test benches using modern verification techniques Implementing functional coverage and assertions using System Verilog and UVM, Developing TB environment using SV and UVM, Developing test and functional coverage plans based on device specifications, Analyzing and debugging simulation failures, as well as analyzing functional coverage results to guarantee zero defect outcomes, Your Profile You are best equipped for this task if you have: Engineering in Electrical/electronic streams , or equivalent experience, 5+ years experience in constrained-random, coverage driven verification environments, Experience in RAL Experience in developing the test bench from scratch using System Verilog (SV) HDVL and UVM (Universal Verification Methodology), Expertise in Gate Level simulations (GLS) and have debugged, root caused real netlist issues, A solid understanding of verification concepts and experience designing class-based test benches, C coding, Formal verification methods and Power aware simulation will be an advantage Excellent written and oral communication skills Strong debugging skills, functional simulations and GLS simulations, Contact: Gowri Shenoy@infineon,, LinkedIn #WeAreIn for driving decarbonization and digitalization, As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals Be a part of making life easier, safer and greener, Are you in We are on a journey to create the best Infineon for everyone, This means we embrace diversity and inclusion and welcome everyone for who they are At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities We base our recruiting decisions on the applicant?s experience and skills, Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process, Click here for more information about Diversity & Inclusion at Infineon,

Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices, Job Description In your new role you will: Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices, Responsible for: Designing self-checking test benches using modern verification techniques Implementing functional coverage and assertions using System Verilog and UVM, Developing TB environment using SV and UVM, Developing test and functional coverage plans based on device specifications, Analyzing and debugging simulation failures, as well as analyzing functional coverage results to guarantee zero defect outcomes, Your Profile You are best equipped for this task if you have: Engineering in Electrical/electronic streams , or equivalent experience, 2+ years experience in constrained-random, coverage driven verification environments, Experience in RAL Experience in developing the test bench from scratch using System Verilog (SV) HDVL and UVM (Universal Verification Methodology), Expertise in Gate Level simulations (GLS) and have debugged, root caused real netlist issues, A solid understanding of verification concepts and experience designing class-based test benches, C coding, Formal verification methods and Power aware simulation will be an advantage Excellent written and oral communication skills Strong debugging skills, functional simulations and GLS simulations, Contact: Gowri ShenoyGowri Shenoy@infineon,, LinkedIn #WeAreIn for driving decarbonization and digitalization, As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals Be a part of making life easier, safer and greener, Are you in We are on a journey to create the best Infineon for everyone, This means we embrace diversity and inclusion and welcome everyone for who they are At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities We base our recruiting decisions on the applicant?s experience and skills, Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process, Click here for more information about Diversity & Inclusion at Infineon,

Salary : 2.2LPA - 14k Change in Hand per month (after deductions of PF,ESI,PT) 2Years Bond & Need to Submit your 10th Original Mark list with us during the Bond Period. Must have a SAS training Certificate. Role & responsibilities: 1. Providing inputs related to statistical methods for various study design ( two way, parallel, replicate, study state etc) and protocol preparation considering the requirements of BE studies for USFDA, EMEA, CANADA etc submission. 2. Preparation of randomization schedule as per the protocols and applicable SOPs for following study designs ( two way, parallel, replicate, study state etc). 3. Data checking for consistency and outlier analysis for bio-analytical data as well as PK data. 4. Perform statistical analysis of PK data using SAS software for different study designs ( two way, parallel, replicate, study state etc) for USFDA, EMEA, CANADA etc submission. 5. Preparation of statistical report and SAP. 6. Provide sample size estimation/ justification. 7. Statistical outlier detection as per the concerned protocol or regulatory requirements. 8. Response preparation for addressing the regulatory queries related to statistical aspects.

Title Our clinical operations activities are growing rapidly, and we are currently seeking a full-time, office-based IRT Validator to join our Randomization and Study Product Management team in Mumbai, India. This position plays a key role in the clinical trial management process at Medpace. If you want an exciting career where you use your previous expertise and can develop and grow your career even further, then this is the opportunity for you. Overview Medpace is a full-service clinical contract research organization (CRO). We provide Phase I-IV clinical development services to the biotechnology, pharmaceutical and medical device industries. Our mission is to accelerate the global development of safe and effective medical therapeutics through its scientific and disciplined approach. We leverage local regulatory and therapeutic expertise across all major areas including oncology, cardiology, metabolic disease, endocrinology, central nervous system, anti-viral and anti-infective. Headquartered in Cincinnati, Ohio, employing more than 5,000 people across 40+ countries. Responsibilities Creation of test plans; Execution of test plans and creation of validation packages; Review of validation packages created by other team members; Review requirement specification documents provided by internal clients; Validation of new projects and changes to existing projects; Qualifications Bachelor’s degree in Math, Computer Science, or related field required; Demonstrated ability to complete validation tasks within defined time frames and to appropriate quality levels; Fluent in English. People. Purpose. Passion. Make a Difference Tomorrow. Join Us Today. The work we’ve done over the past 30+ years has positively impacted the lives of countless patients and families who face hundreds of diseases across all key therapeutic areas. The work we do today will improve the lives of people living with illness and disease in the future. Medpace Perks Flexible work environment Competitive compensation and benefits package Competitive PTO packages Structured career paths with opportunities for professional growth Company-sponsored employee appreciation events Employee health and wellness initiatives Awards Recognized by Forbes as one of America's Most Successful Midsize Companies in 2021, 2022, 2023 and 2024 Continually recognized with CRO Leadership Awards from Life Science Leader magazine based on expertise, quality, capabilities, reliability, and compatibility What to Expect Next A Medpace team member will review your qualifications and, if interested, you will be contacted with details for next steps.

Education: Bachelor's Degree (BE / BTech) or Master's Degree (ME / MTech) Job Description ASIC Verification Lead Summary of the offer: Integrating ASIC functional verification team. ASIC developed include network controller, router and cache coherence controller targeting Bull high-end servers and Bull high-performance ("big data" and "exascale" servers). Using Constraint-Random, Coverage Driven functional verification methodologies underlying UVM verification framework to ensure full and effective verification of complex ASIC. Main responsibilities: Acquire knowledge of the architecture and microarchitecture of the ASIC by studying specifications and interacting with the architecture and logical design teams. Participate in defining overall verification strategies and methodologies, and the required simulation environments. Develop, maintain and publish verification specifications. Write and perform closely test plans with the logical design team. Develop coverage models and verification environments using UVM-SystemVerilog / C ++ Monitor, analyze and debug simulation errors. Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time. Submit recommendations on tools and methodologies to develop to improve productivity. Mentor junior engineers on how to produce a maintainable and reusable code across projects. Skills: Participated in the successful verification of a complex SoC or ASIC. Mastering UVM or equivalent verification methodology. Proficient developer of Constraint-Random / Coverage-Driven verification environments in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp / SVA) Strong knowledge of simulation tools and coverage database visualization tools Developed test plans that helped identifying sharp functional defects. efficiency in problem solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints Experienced in improving processes and methodologies Experience in managing tasks for a small team. Required minimum experience: 7 years Required minimum studies: Master/Engineer in Electronics and Communication Engineering.