DFT Design Engineer -Memory Team Samsung

5.0 - 8.0 years

5 - 8 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

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Roles and Responsibilities Good Experience in Top/Block, FLAT/Hier DFT insertion flow methodologies Executed scan & MBIST insertion, ATPG and verification at full chip level Experience in timing closure in DFT modes - understanding of shift, capture timing constraints, MBIST constraints and their impacts Generate, review and validate DFT constraints to achieve timing closure of high speed design Experience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations) Exposure to analog and mixed signal IP tests such as PLLs, MIPI etc., methods of their pattern generation and verification Exposure to post-silicon bring-up. Diagnosis and debug methods to arrive at fail points for logic or memory tests Should be able to comprehend architecture and associated limitations with respect to DFT and be able to predict the schedule, amount of task and personnel involved Understanding of Power Estimation/Management for DFT modes is preferred Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples Strong written and oral communication skills Experience 5+ Years Qualifications B.Tech/B.E/M.Tech/M.E

Posted 1 week ago

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R&D Engineering, Sr Engineer Synopsys

1.0 - 5.0 years

3 - 11 Lacs

Bhubaneswar, Odisha, India

On-site

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What You ll Be Doing: * Serving as the single point of contact for post-silicon debug activities. * Enabling Product Requirement Documents (PRDs). * Working to enable IP as a product development platform. * Handling hands-on post-silicon test setups. * Collaborating on top-level physical design, board-level, and package-level designs. * Developing post-silicon reports and conducting debug analysis. The Impact You Will Have: * Driving the successful development and deployment of PVT IP sensors. * Enhancing the reliability and performance of Synopsys silicon lifecycle monitoring solutions. * Ensuring high-quality product development through meticulous testing and debugging. * Contributing to the continuous innovation in chip design and software security. * Supporting Synopsys leadership in the market for PVT IP developments. * Empowering the creation ofhigh-performance silicon chips used in various advanced technologies. What You ll Need: * Hands-on experience in post-silicon test setups. * Sound knowledge of Digital/AMS chip design and post-silicon debug. * BS or MS degree in Electrical Engineering with 3+ years of experience. * Understanding of top-level physical design, board-level, and package-level designs. * Expertise in RTL development and physical design. Who You Are: * Strong communicator with excellent teamwork and interpersonal skills. *Detail-oriented with a mindset geared towards IP debug anddocumentation. * Proactive learner with the ability to adapt to new IPfunctionalities. * Effective leader with strong people management skills. * Highly motivated and capable of mentoring both internal teams and external customers.

Posted 3 weeks ago

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