Analog Layout Design Engineer Synopsys (India) Private Limited

2.0 - 4.0 years

2 - 4 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

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Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Creating floorplans, routing, and performing physical verifications to meet quality standards. Debugging and solving complex layout issues to ensure high-quality deliverables. Collaborating with design engineers to optimize layout for performance, power, and area. Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. Ensuring compliance with DRC, LVS, ERC, and antenna rules. The Impact You Will Have: Contribute to the development of cutting-edge technologies that drive the Era of Smart Everything. Enhance the performance and reliability of next-generation semiconductor IPs. Accelerate the time-to-market for high-performance silicon chips. Reduce risks associated with layout design by adhering to stringent verification requirements. Foster a collaborative and innovative work environment. Support Synopsys mission to lead in chip design and software security. What You'll Need: BTech/MTech in Electrical Engineering or related field. 2+ years of relevant experience in analog layout design. Proficiency in developing quality layouts and performing physical verifications. In-depth understanding of deep submicron effects and floorplan techniques. Experience with CMOS, FinFET, and GAA process technologies at 7nm and below. Knowledge of layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation.

Posted 2 weeks ago

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Analog layout design,Staff Engineer Synopsys (India) Private Limited

4.0 - 6.0 years

4 - 6 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Foundit logo

Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Solving complex problems and debugging issues effectively. Executing layout floorplanning, routing, and physical verifications to meet stringent quality requirements. Ensuring compliance with DRC, LVS, ERC, and antenna rules. Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below). Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. The Impact You Will Have: Enhancing the performance and reliability of Synopsys DDR/HBM/UCIe IPs. Accelerating the integration of advanced capabilities into SoCs. Reducing risk and improving time-to-market for differentiated products. Driving innovation in semiconductor technology and design. Contributing to the success of Synopsys Silicon IP business. Fostering a collaborative and inclusive work environment. What You'll Need: BTech/MTech degree in a relevant field. 4+ years of experience in analog layout design. Proven track record in developing high-quality layouts and meeting verification timelines. Strong understanding of deep submicron effects and floorplan techniques. Exposure to layout matching, ESD, latch-up, EMIR, DFM, and LEF generation.

Posted 2 weeks ago

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Analog layout design Synopsys (India) Private Limited

4.0 - 6.0 years

4 - 6 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Foundit logo

Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Solving complex problems and debugging issues effectively. Executing layout floor planning, routing, and physical verifications to meet stringent quality requirements. Ensuring compliance with DRC, LVS, ERC, and antenna rules. Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below). Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. The Impact You Will Have: Enhancing the performance and reliability of Synopsys DDR/HBM/UCIe IPs. Accelerating the integration of advanced capabilities into SoCs. Reducing risk and improving time-to-market for differentiated products. Driving innovation in semiconductor technology and design. Contributing to the success of Synopsys Silicon IP business. Fostering a collaborative and inclusive work environment. What You'll Need: BTech/MTech degree in a relevant field. 4+ years of experience in analog layout design. Proven track record in developing high-quality layouts and meeting verification timelines. Strong understanding of deep submicron effects and floorplan techniques. Exposure to layout matching, ESD, latch-up, EMIR, DFM, and LEF generation.

Posted 2 weeks ago

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