5.0 - 9.0 years

0 Lacs

karnataka

On-site

The position at Samsung Semiconductor India Research (SSIR) requires a Senior DFT Engineer with at least 5 years of experience in full chip DFT architecture, implementation, timing closure, and post-silicon validation. As part of the team, you will be responsible for various key tasks including scan architecture planning, pin mixing, scan compression planning, and optimization for pattern volume for SA and TD pattern sets. Your expertise will be crucial in scan synthesis, power optimization techniques in test modes, MBIST architecture planning, repair architectures, insertion, verification, and analog and mixed signal IP testing architecture and verification. In this role, you will also be involved in timing closure of scan, MBIST, and other test modes, writing SDCs, understanding timing exceptions, debugging timing issues with the PD team, performing timing GLS, and debugging fails in simulations. Post-silicon validation, interpretation of tester results, debugging IR drop issues, and diagnostics of silicon failures will also be within your scope of responsibilities. Understanding of JTAG operation and debug is required, with knowledge of iJTAG protocol being desirable. Additionally, you will need to understand functional test cases, IO testing, and testing of ARM processor cores. As a Senior DFT Engineer, you must demonstrate the ability to lead a team across all aspects of DFT, interact effectively with RTL and physical design teams for DFT implementation, anticipate risks, plan project timelines, and milestones. The role requires a Bachelor's or Master's degree in Engineering with 5+ years of relevant experience. Samsung Semiconductor India Research (SSIR) values diversity and is committed to providing Equal Employment Opportunity to all individuals, irrespective of their religion, gender, age, marital status, gender identity, veteran status, genetic information, disability status, or any other characteristic protected by law.,

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