15 Icc2 Jobs

As a Senior Physical Design Engineer, you will be responsible for leading the Netlist-to-GDSII implementation process on advanced submicron technology nodes. Your expertise in utilizing industry-standard EDA tools and your understanding of timing closure and physical verification will be crucial for this role. Your key responsibilities will include driving the entire Netlist-to-GDSII flow, which involves tasks such as floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. You will also be required to conduct Static Timing Analysis (STA) to ensure timing closure across all design corners, as well as execute power integrity and physical verification checks (LVS, DRC). Collaboration with cross-functional teams including RTL, STA, packaging, and DFT will be essential to successfully handle complex designs on 28nm and below technology nodes. To excel in this role, you must possess strong hands-on experience with tools such as Synopsys/Cadence Innovus, ICC2, Primetime, PT-PX, and Calibre, along with a solid understanding of Physical Design Methodologies including Floorplanning, Placement, CTS, Routing, and STA. Proficiency in timing constraints and closure, Tcl/Tk/Perl scripting, and working with submicron nodes (28nm and below) are also essential skills required for this position. While not mandatory, familiarity with Fusion Compiler, a broader understanding of signal and power integrity, as well as experience in workflow automation and tool scripting would be considered advantageous for this role. If you are excited about the prospect of taking on this challenging and rewarding opportunity, we encourage you to submit your resume to hemanth@neualto.com or spoorthy@neualto.com to express your interest.,

As a VLSI Mentor / Guest Faculty specializing in Advanced Digital Systems & Low Power Design at Spandsons Horizon Engineering, you play a crucial role in guiding 5th, 6th, and 7th-semester B.E./B.Tech students in advanced VLSI concepts and practical applications. This contract role, based in Salem, offers a unique opportunity to directly influence the academic and career growth of 60 aspiring engineers. Your key responsibilities include delivering engaging sessions covering topics such as Advanced Digital System Design with Verilog HDL and Low Power VLSI Design. You will also provide hands-on guidance for lab assignments and projects using various tools like Xilinx Vivado, ModelSim, LTspice, and more. Facilitating interactive learning and ensuring alignment with the semester curriculum are essential aspects of this role. To qualify for this position, you need a minimum of 4-5 years of industry experience in VLSI design, proficiency in relevant EDA tools and hardware platforms, excellent communication skills, and a passion for teaching and mentoring. The program details include a total of approximately 60 students, with sessions scheduled on Thursdays and Fridays for 12 hours per week starting on July 24th & 25th. The program will run for Semesters 5, 6, and 7. In addition to a comprehensive program, benefits such as accommodation, food, and the opportunity to impact the next generation of VLSI engineers are provided. Join us at Spandsons Horizon Engineering and be part of a forward-thinking academic institution.,

Tenstorrent is at the forefront of AI technology, setting new standards in performance, usability, and cost efficiency. With the evolution of AI reshaping computing, there is a growing need for innovative solutions that integrate advancements in software models, compilers, platforms, networking, and semiconductors. Our team comprises diverse technologists who have created a high-performance RISC-V CPU and share a common passion for AI, striving to develop the ultimate AI platform. We value collaboration, curiosity, and a dedication to solving complex problems. As we expand our team, we are seeking individuals at all levels to contribute to our mission. We are currently seeking an experienced engineer to lead the clock design efforts for our IP, CPU, and SoC teams. In this role, you will be responsible for defining clocking strategies that strike a balance between stringent timing requirements, power efficiency, and area constraints. You will collaborate closely with RTL, PD, and power engineers to construct robust, high-performance systems. This position is based in Bangalore and requires onsite presence. We invite candidates with a minimum of 6 years of experience to apply for this role. Throughout the interview process, candidates will be evaluated for their proficiency, and job offers will be made based on the assessment, which may vary from the details provided in this listing. As an ideal candidate: - You possess a solid background in clock tree synthesis and clock network design. - You are adept at working with timing, CDC, and low-power design methodologies. - You have experience working with advanced technology nodes, particularly 5nm or below, influencing design decisions. - You enjoy developing scripts to automate tasks and streamline engineering workflows. Key responsibilities include: - Taking charge of the end-to-end clock architecture for intricate SoCs. - Collaborating effectively with RTL, physical design, and power teams to achieve project objectives. - Proficiency in utilizing tools like Synopsys FC, ICC2, and scripting languages such as Python, Perl, or Tcl. - Demonstrating a problem-solving mindset focused on enhancing efficiency and resilience. This role offers the opportunity to: - Architect clocking strategies that are scalable across IP, CPU, and SoC designs. - Learn techniques to minimize power consumption and jitter while meeting aggressive power, performance, and area (PPA) targets. - Enhance workflows and reduce manual interventions through intelligent automation. - Address and resolve challenges specific to cutting-edge technology nodes. Join us at Tenstorrent and be part of a dynamic team dedicated to pushing the boundaries of AI technology.,

You should possess in-depth knowledge and hands-on experience in Netlist2GDSII Implementation, including tasks such as Floorplanning, Power Grid Design, Placement, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), Power Integrity Analysis, Physical Verification, and Chip finishing. It is essential to have experience with Physical Design Methodologies and sub-micron technology, particularly in 16nm and lower technology nodes. Moreover, you should have expertise in Analog and Mixed Signal Design and be familiar with handling designs with more than 5M instance count and operating at a frequency of 1.5GHz. Proficiency in programming languages such as Tcl, Tk, and Perl is required to automate the design process and enhance efficiency. Hands-on experience with PnR Suite from Cadence & Synopsys, specifically Innovus & ICC2, is a must. Additionally, you should have a strong background in Static Timing Analysis using tools like PrimeTime for SI analysis, EM/IR-Drop analysis with PT-PX and Redhawk, as well as Physical Verification using Calibre. Understanding the practical application of methodologies, Physical Design Tools, Flow Automation, and driving improvements in these areas is highly beneficial. Experience in complex SOC integration, Low Power and High-Speed Design, as well as proficiency in Advanced Physical Verification Techniques, are desirable skills for this role.,

HW Physical Design macros with Innovus and ICC2 tools. block implementation such as floorplanning, placement, clock tree synthesis, routing and optimization. signoff closure related fixes and runs ,formal verification and physical verification.

Job Specs : We are seeking a highly skilled and motivated ASIC Physical Design Experts to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Design IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location and Expertise: Bangalore : 4 Years 15 Years Beijing : 8 Years 10 Years Chennai : 3 Years 6 Years Vietnam : 8 Years 10 Years Taiwan : 8 Years 10 Years Desired Profile : Bachelor's / Master's degree in engineering from EEE / E&C / VLSI with 3+ Years of work expertise in ASIC Physical Design Expertise in managing, mentoring and training team of ASIC physical design engineers working across different time zones, this is mandatory for lead positions Expertise in ASIC PD. Expertise in digital physical design Expertise in working with 3nm & 5nm technology nodes Expertise in EDA synthesis, APR, STA tools and methodologies Expertise in one or more of the following tools ICC, ICC2, Innovus, Olympus Working knowledge of one or more of the following tools Primetime, Calibre, and Red hawk Expertise in working with multi modes and multi corners STA Working Knowledge of multiple power planes and multiple VT libraries Basic domain knowledge of EM, IR, RV analysis, Noise and Formal Equivalence Verification Good at scripting languages PERL, TCL, shell Worked on at least 2 tape ins of moderate to high speed designs with multiple power planes Debug, fix, and validate pre- and post-silicon IP/sub-system logic issues and bugs Expertise in one or more of the following circuit design fields is an advantage: clock tree optimization, Timing analysis, and Power optimization Expertise in making ECOs both Metal and logic level ecos Expertise in DRC and LVS cleanup of designs during sign off Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit.

Strong desire to learn and explore new technologies. Demonstrates good analysis and problem-solving skills. Prior knowledge and experience in tools like DC, ICC2, PT-SI, FC is a definite advantage. Should be a strong team player, excellent communicator as the role involves daily technical interaction with local, US counterparts. What You'll Be Doing: He/She will be part of SNPS DDR/HBM/Ucie IP implementation team and responsible for the implementation and integration of world class DDRs at the cutting-edge technology nodes. Timing closure above 4GHz, mixed signal hard macro IP integration, building efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job. Prior working knowledge in the DDR/HBM/HBI timing closure, implementation would be an added advantage. Should be very hands-on and able to technically lead a team of 4-6 junior engineers towards successful completion of project on-time and with top quality. Who You Are: Typically requires a minimum of 6+ years of related experience after post-graduation. Possesses a full understanding of specialization area plus working knowledge of multiple related areas. A team player who independently resolves a wide range of issues in creative ways on a regular basis. Customarily exercises independent judgment in selecting methods and techniques to obtain solutions. Performs in project leadership role. Contributes to complex aspects of a project. Determines and develops approach to solutions. Work is independent and collaborative in nature. Provides regular updates to manager on project status. Represents the organization on business unit and/or company-wide projects. Guides more junior peers with aspects of their job.

Providing Customer Support and Collaborating with R&D teams to drive product development for wide deployment. Demonstrating differentiated PPA results to showcase our technologys superiority. Providing technical support to key global customers to address PPA bottlenecks and design challenges on the most advanced designs. Aggressively engaging in worldwide critical benchmarks and deployments to ensure the highest quality and performance of designs. Utilizing scripting languages such as Perl and Tcl for automation and optimization tasks. Staying updated with the latest advancements in ASIC design flow, VLSI, and CAD development to continually improve processes. The Impact You Will Have: Enhancing the performance and efficiency of Fusion Compiler designs. Driving innovations that contribute to the success of Synopsys cutting-edge technologies. Providing critical support that helps key customers overcome their PPA challenges. Contributing to the development of new features that keep Synopsys at the forefront of the industry. Improving the overall quality and reliability of our products through meticulous design and optimization. Fostering strong relationships with global customers, reinforcing Synopsys reputation as a leader in chip design and software security. What You ll Need: BS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience. Hands-on experience with synthesis and place and route (P&R) tools. Proficiency with EDA tools such as DC, FM, ICC2, and Fusion Compiler. Knowledge of advanced placement and routing rules. Experience with scripting languages like Perl and Tcl. Strong understanding of ASIC design flow, VLSI, and CAD development. Never give-up attitude and flexibility in supporting worldwide engagements. Who You Are: Excellent communicator with strong command of English. Highly motivated and self-driven. Detail-oriented with a focus on quality and performance. A team player who thrives in collaborative environments. Adaptable and eager to learn new technologies and methodologies.

What Youll Need: BS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience, Hands-on experience with synthesis and place and route (P&R) tools, Proficiency with EDA tools such as DC, ICC2, and Fusion Compiler, Knowledge of advanced placement and routing rules, Experience with scripting languages like Perl and Tcl, Strong understanding of ASIC design flow, VLSI, and CAD development, Never give-up attitude and flexibility in supporting worldwide engagements, Who You Are: Excellent communicator with strong command of English, Highly motivated and self-driven, Detail-oriented with a focus on quality and performance, A team player who thrives in collaborative environments, Adaptable and eager to learn new technologies and methodologies,

What Youll Need: BS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience, Hands-on experience with synthesis and place and route (P&R) tools, Proficiency with EDA tools such as DC, ICC2, and Fusion Compiler, Knowledge of advanced placement and routing rules, Experience with scripting languages like Perl and Tcl, Strong understanding of ASIC design flow, VLSI, and CAD development, Never give-up attitude and flexibility in supporting worldwide engagements, Who You Are: Excellent communicator with strong command of English, Highly motivated and self-driven, Detail-oriented with a focus on quality and performance, A team player who thrives in collaborative environments, Adaptable and eager to learn new technologies and methodologies,

Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level) Active participation in post silicon validation, correlation and test activities using in-house test and validation lab Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Quartz, Calibre, internal tools & flow Perform custom RF Physical Design, including block-level and top level layouts, floorplanning, package routing Supports complex projects or leads smaller independent design activities Support CAD and drawing updates on both sustaining/new project with minimal supervision Contributes to PD architecture/Plug-In Unit at the unit level

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 15 years or MSEE/CE + 12 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 15 years or MSEE/CE + 12 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Staff Physical Design Engineer • Job Description o Be part of a diverse team working on the high performance designs. Youll lead the complex multimillion instance subsystems including high-speed blocks i.e. DDR, PCIe, AI Cores • Technical Requirements o 8-12 years of experience in Physical Design o Expert in PnR, sign off convergence including timing, physical and PDN verification o Experience in sub 5nm technology node with high performance designs o Experience in pushing performance by custom PnR techniques o Expert of STA and eco generation PnR steps o Expert in debugging and fixing flow, tool and design related issues independently o Experience in the solving physical integration design challenges o Expertise in industry standard tools like Innovus/ICC2/Fusion compiler/Primetime o Experience in contributing to physical design flows and methodologies o Expertise in automation scrips(TCL/PERL/Python)for various implementation steps o Experience in leading and mentoring a team o Ability to work cross-functionally with various teams • Academic Credentials o Qualification: Bachelors or Masters in Electronics/Electrical Engineering

Staff Power Delivery Network and Reliability Engineer Mulya Technologies Greater Bengaluru Area (Hybrid) Staff Power Delivery Network and Reliability Engineer Bangalore Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Power Delivery Network and Reliability Engineer Expertise in Power Grid design and in-depth knowledge of IR drop & EM(electromigration) concepts Knowledge of PDN tool algorithms and hands-on experience with industry-standard tools like Voltus and Redhawk/Redhawk-SC, Exposure to implementation tools like Innovus/ICC2 is a plus Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"