3.0 - 7.0 years

0 Lacs

hyderabad, telangana

On-site

As a Senior RTL Design Engineer with 3-5 years of experience, you will be based in Hyderabad. You will be required to demonstrate strong RTL (Verilog/System Verilog) skills with a focus on IP development. Your responsibilities will include verifying designs by creating simple testbenches, as well as possessing a solid foundation in logic synthesis and timing closure concepts. Additionally, you should have a good understanding of SoC architecture, AXI bus protocols, and hardware debug processes. Experience with Xilinx FPGAs, Vivado tool flows, and micro-architecture development will be considered a plus. If you meet the specified requirements and are interested in this opportunity, please submit your updated resume to janagaradha.n@acldigital.com.,

Posted 1 week ago

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