Name: Jobpe
Address: T-Hub, Plot No 1/C, Sy No 83/1, Raidurgam panmaktha, Knowledge City Rd, Hyderabad, Telangana, 500081, IN
Telephone: +91-83339-09630
Price range: Free

ASIC Verification lead Jemysto Tech

8.0 - 12.0 years

0 Lacs

tamil nadu

On-site

As the SOC Verification Lead, you will be responsible for coordinating with SOC (Design, DFT, PD), System, and SW engineering teams to drive and lead SOC verification execution. You will take ownership of multiple SOC verifications within the targeted functional domain. Your role will involve collaborating with customers on feature requirements, use case scenarios, and test plan reviews to ensure that the SOC meets all functional aspects of the targeted domain. Additionally, you will work closely with the architecture and design team on high-level architecture and use case scenarios, as well as the configuration space. Collaboration with the IP team for IP requirements and deliverables will be a key aspect of your responsibilities. You will also engage with vendors and ODC members to ensure successful project execution. Your role will require working with the program management team on SOC planning, schedule management, resource demand/supply, critical path analysis, development cost, and execution. Furthermore, you will collaborate with the post-Si team to drive Si bring-up and ramp to productization. As a Pattern Verification Manager, you will leverage your expertise in Patterns/Crest functional domains. Your duties will include developing patterns, verifying them, and delivering patterns to the Product Engineering team for silicon validation. You will be responsible for creating test plans for the patterns at the SOC level, and ensuring they are reviewed with stakeholders. Collaboration with the IP design team for IP requirements and deliverables, as well as working with the program management team for Patterns planning, schedule management, critical path analysis, and execution, will also be part of your responsibilities. You will be driving SOC verification from feature extraction to tape-out and productization. Adapting to design changes, leading Verification Architecture, test-plan creation, power reduction, timing convergence, test bench and test plan reviews, and tape-outs will be crucial aspects of your role. Running regular execution meetings, scrums, standing meetings, and resolving bottlenecks will be essential for successful project outcomes. Additionally, you will be involved in project planning, including scheduling, deliverables, risk assessment, and mitigation strategies. Your leadership will be pivotal in driving the team towards bug-free silicon deliverables.,

Posted 4 days ago

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