Sr. Staff Silicon Validation Engineer Lattice Semiconductor

12.0 - 16.0 years

0 Lacs

pune, maharashtra

On-site

As a Silicon Design Validation Engineer at Lattice, you will have the opportunity to be part of a dynamic team working on cutting-edge FPGA projects. This role involves validating building blocks in FPGA on the board level to ensure functionality and performance according to design intent. The FPGA includes various IPs such as SERDES (PMA/PCS), Memory DDR (DDR4, LPDDR4, DDR5, etc.), DPHY, PLL, DSP, Fabric, I/O, among others. In this position, you will learn how to validate one or many building blocks within the FPGA and gain knowledge of the process and methodology required for validating IPs from planning to completion. You will work with advanced equipment, boards, and software/tools while developing validation and characterization plans for specific IPs, bench hardware, and software. You will also create test logic RTL to conduct validation and characterization tests, drive new silicon product bring-up, validation, and debug processes, and analyze data sheet parameters. The ideal candidate for this role is highly motivated to develop a career in Silicon Design Validation Engineering. You will have exposure to various areas including FPGA and its building blocks, IP validation, bench hardware and software development, and more. You will lead and manage teams, possess an electrical engineering degree, have expertise in high-speed Serdes interface characterization, high-speed board design, Verilog/VHDL, FPGA development tools, test automation development, statistical analysis concepts, and bench equipment for device characterization. To excel in this role, you should have strong written and verbal communication skills, be self-motivated, proactive, possess critical thinking skills, and demonstrate good problem-solving and debugging abilities. If you thrive in a fast-paced, results-oriented environment and are looking to contribute to a team-first organization, Lattice may be the perfect fit for you.,

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Verification Engineer Indian Institute of Technology Delhi (IIT Delhi)

6.0 - 11.0 years

30 - 45 Lacs

Hyderabad

Work from Office

Develop verification testbench components for chip/module level using System Verilog, C/C++. Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment. Define and execute detailed verification plan from spec working with architects, designers, system engineers. Write tests, Debug tests, automate regression scripts and regression environment. Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout. Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required. Excellent debugging skills in both SW and ASIC hardware. Must be good in building verification environments preferably using Verilog, System Verilog, UVM, C/C++/PLI etc. Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus. Experience with simulators like ncVerilog (Incisive), VCS, Eldo and debug tools like Verdi/Debussy. Good understanding of latest formal verification techniques, assertions, properties is a plus. Understanding or prior experience with Industry standard protocols like USB/SPI/SATA/Ethernet/DisplayPort/SRIO/DDR/PCIE/DDR4/LPDDR4/DFI etc is a definite plus. Understanding or Prior Experience in ARM/Tensillica Processor platforms is a definite plus. Good written and oral communication skills. Ability to clearly document plans.

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