Staff Design Verification Analog Devices

7.0 - 11.0 years

0 Lacs

karnataka

On-site

As a Design Verification Engineer, you will be responsible for verifying complex designs such as accelerators, datapath IP, processor core subsystems, and complex interfaces/protocols using leading-edge methodologies like UVM and Formal DV. Your role will involve architecting the testbench, developing the verification environment, and defining test plans, tests, and verification methodology for block/sub-system level verification. You will collaborate with the design team to generate test plans, ensure code and functional coverage closure, integrate block testbenches at the sub-system level UVM environment, and verify integration. Additionally, you will interact with the analog co-simulation and firmware team to enable top-level chip verification aspects. Your responsibilities will also include packaging verification environments for Digital IP for seamless integration into the verification flow at different stages of execution. You will evaluate 3rd party IPs on key qualitative aspects and establish evaluation flows for home-grown and 3rd party IPs for consistent benchmarking of DV evaluation. To excel in this role, you should have a minimum B.E./B.Tech degree in Electrical/Electronics/Computer Science and 7-10+ years of experience in design verification with UVM and constrained random, coverage-based verification approaches. You must possess a strong understanding of DV concepts and the ability to develop scalable DV environment architecture for achieving first-pass DV success. Your adaptability to learn end application/systems and map them into smart verification test plans will be crucial. Excellent debugging and analytical skills, along with good interpersonal, teamwork, and communication skills, are essential for effectively driving discussions with geographically dispersed teams. Knowledge of assertion-based formal verification, standard on-chip interfaces, processor/SoC architecture, and/or DSP fundamentals will be advantageous. Experience with ASIC/SoC product DV and productization is highly desirable for this role.,

Posted 4 days ago

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FPGA Design and Verification/Validation Engineers Dexcel Electronics

2.0 - 6.0 years

0 Lacs

karnataka

On-site

As an FPGA Design and Verification/Validation Engineer at Dexcel Electronics in Bengaluru or Hyderabad, you will be responsible for independently overseeing FPGA Design Blocks. You should have a minimum of 2 years of experience in RTL Design, 2 years in IP Verification, 4 years in IP Design/SOC Design, and 6 years in FPGA Design. Your primary task will involve working with various Interfaces such as PCIe 2.0, SATA, Fiber Channel, 1G/10G BASE, MII/RMII/GMII/RGMII/SGMII/XAUI, RXAUI, SDI- SD/HD/3G, Display Port, USB, JESD204B, SRIO, MIPI, DDR/LPDDR/DDR2/DDR3, and QDR memories. Additionally, hands-on experience in Design and Debugging is preferred. You should have prior experience working on projects based on FPGAs and SOC, with a solid understanding of SOC and Hi-Speed Interfaces domain knowledge. At Dexcel Electronics, we are seeking highly motivated individuals who are eager to learn and develop in a dynamic environment. If you are passionate about technology and seeking exciting career opportunities, we invite you to join our team. For more information on current job openings, please visit our website or email your updated resume to careers@dexceldesigns.com.,

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ASIC SOC & GLS Verification Engineer Vhunt4u

7.0 - 10.0 years

25 - 40 Lacs

Noida, Bengaluru, Delhi

Work from Office

Job Specs : We are seeking a highly skilled and motivated ASIC SOC & GLS Verification Engineer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Verification IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Remote, Work From Anywhere Work Expertise: 7 Years 10 Years Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. Expertise in ASIC SOC verification. Expertise in UVM, System Verilog and constrained random testing. Expertise in Gate Level Simulation tools (GLS) or verification related to display port or memory controller Expertise in testbench architecture and SOC-level verification strategies. Knowledge of scripting languages (Python, Perl, TCL) for automation. Good understanding of SoC architecture, including CPU subsystems, memory hierarchy, and peripherals. Preferred immediate hires only Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Posted 1 month ago

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