CPU Core Validation Engineer

As a CPU Core Validation Engineer, you will be an integral part of the CPU Validation team within the CPU organization, focused on validating CPU core pipeline architecture and microarchitecture features. Your responsibilities will include developing a detailed test plan that takes into consideration the IP architecture and microarchitecture features. You will collaborate closely with CPU design and verification teams to create CPU bring-up and functional validation test plans for the IP you are responsible for. Additionally, you will design validation methodology and test content to be utilized on emulators during the pre-silicon phase as well as on actual silicon. Working with SOC bring-up and software teams, you will strategize CPU core feature bring-up and conduct end-to-end validation. In case of failures on silicon, you will be responsible for triaging and debugging issues. Furthermore, you will develop test content and testing strategies to support CPU validation on silicon and collaborate with CPU verification teams to replicate silicon failures on emulators and FPGAs. You will also engage with the design team to propose and design new debug features to enhance future CPU bring-ups. The minimum requirements for this role include a BA/BS degree in Computer Science or Electrical Engineering with at least 5 years of experience. You should have a minimum of 3 years of experience in Silicon Validation and bring-up. Proficiency in implementing assembly and C/C++ language embedded firmware is essential, along with familiarity with software toolchains such as assemblers, C compilers, Makefiles, and source code control tools. Preferred qualifications for this position include a strong understanding of microprocessor architecture, particularly in areas like Cache Coherence, Memory Ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative Execution, and Address Translation/Memory Management. Knowledge of Random Instruction Sequencing (RIS) and testing at both the Block/Unit-level and Subsystem/Chip-level is beneficial. Experience in creating test plans and writing Assembly code is desirable, as well as the ability to independently develop and work on a block/unit of the design.,