Singapore Payroll Processor (ECP) Teamware Solutions

5.0 - 10.0 years

11 - 20 Lacs

Bengaluru

Hybrid

Key Responsibilities: Payroll Operations: Execute payroll operations in compliance with procedures, regulations, and customer requirements Process payroll data in accordance with legal and data protection standards. Ensure timely and accurate payroll processing and validation of transactions. Contribute to SOPs, training materials, and policy updates. Monitor quality, provide feedback, and participate in process improvements. Process payroll payments and initiate treasury releases. Collaborate with the Country Lead on local authority queries. Support accounting functions and manage payroll-related queries. Communicate risks and report payroll activity status. Support year-end and country-specific processes. Assist with internal and external audits. Support continuous improvement initiatives. Payroll Customer Service: Deliver high-quality service in help desk operations with accurate, timely resolution of queries. Engage in continuous improvement of customer service. Maintain updated help desk scenarios. General: Act as a backup for the Payroll Country Manager as needed. Stay updated on processes and country-specific information through training. Serve as a backup for team members and additional functions as assigned. Train others through assigned courses and work shadowing. Statutory Compliance: Ensure timely payment and submission of statutory requirements (CPF, IR21, IR8A). Administer tax-related submissions to IRAS. Manage claims for childcare, maternity, paternity leaves, and NS Make-Up Claims. Mandatory Skills: Extensive knowledge of Singapore legislative requirements. End-to-end payroll processing experience. Nice to Have Skills: Experience with ECP Payroll System.

Posted 4 weeks ago

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SOC Power Design -Sr Eng/Sr Lead/Staff/Sr Staff Qualcomm

4.0 - 9.0 years

20 - 25 Lacs

Hyderabad

Work from Office

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Posted 1 month ago

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Physical Design Engineer HCLTech

5.0 - 10.0 years

10 - 20 Lacs

Hyderabad, Chennai, Bengaluru

Work from Office

Role & responsibilities Physical Design Engineer (PD/STA/Synthesis) Must-Haves: •Tools: Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime for STA •Flow Experience: •Floorplanning •Power planning •Placement •Clock Tree Synthesis (CTS) •Routing •Physical Verification (DRC/LVS) •Timing Closure •Knowledge of: •Low-power design (UPF/CPF) •ECOs •IR Drop, EM Analysis •STA constraints and timing analysis Nice-to-Haves: •Experience with block-level and/or full-chip PD •Familiarity with scripting (Tcl, Perl, Python)

Posted 1 month ago

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