4 Coverage Closure Jobs

Own and develop UVM-based testbench environments for IP/SoC verification Design verification architecture, testplans, and SVA based on protocol specifications (PCIe, CXL, UCIe, AXI, etc.) Drive all aspects of the verification lifecycle including testbench creation, coverage closure, and debugging Collaborate with RTL design teams to resolve issues and close functional coverage Conduct peer reviews to maintain high testbench code quality Contribute technical papers and patent ideas on testbench innovations and verification methodologies Work closely with global teams and ensure timely project execution The Impact You Will Have: Deliver reliable and robust verification solutions that ensure high-quality IP/SoC design Influence UVM testbench architecture through innovation and best practices Improve efficiency and accuracy in verification through SVA and advanced debugging Enable faster time-to-market by streamlining simulation and debug processes Contribute to Synopsys IP leadership by ensuring verification excellence across global projects What You'll Need: 48 years of experience in UVM-based verification for IP/SoC Strong SystemVerilog knowledge and protocol understanding (PCIe, CXL, UCIe, AXI, etc.) Hands-on experience with functional coverage closure and SystemVerilog Assertions (SVA) Proficiency in simulation tools and waveform debug tools like DVE/Verdi Familiarity with version control tools (e.g., Perforce) Scripting knowledge (Python, TCL) is an added advantage Strong communication, problem-solving skills, and ability to work across teams and geographies

BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas: Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI, APB, AHB) etc Good knowledge of System Verilog Hands-on experience with coverage closure and writing SVA for IP/SOC Good simulation debugging skills Experience with Perforce or similar revision control environment Experience with Python/TCL or any scripting knowledge is an added advantage Job Responsibilities include - Understand Standard Specifications, create testplan for the product and create UVM based testbench architecture. Propose and enhance the UVM architecture with unique idea for verification Be single point of contact with hands-on experience on all verification tasks Testbench Creation Testplan creation Coverage closure SVA Release Perform peer review of testbench code for continuous quality Own simulation debugs using DVE/Verdi, interact with Design Team and aid in debug and Verification closure The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide Lead team of engineers to perform various verification activities on IPs/Subsystems Anticipate problems and risks and work towards a resolution and risk mitigation plan Assist and mentor the team in day-to-day activities and grow the capabilities of verification team for future assignments Review various results and reports to provide continuous feedback to the team and improve quality of deliverables Report status to management and provide suggestions to resolve any issues that may impact execution The candidate must have excellent oratory and written communication skills in English, should be a team player and possess good problem-solving skills and show high levels of initiative

Responsibilities: Manage territory sales performance Close deals through effective negotiation Develop new business opportunities Maintain customer relationships Meet revenue targets

The candidate will be part of the Synopsys CXL IP Design verification R&D team at Synopsys. You will own UVM based verification environment, which handles multiple features of IP, test plan creation, test case writing, random constraint creation, coverage closure, SVA and Release. As part of the work, you will closely work with lead and be part of a global team of experienced Engineers. Technical Expertise Needed: BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas: Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP/SoC. Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI,APB,AHB) etc Good knowledge of System Verilog. Hands-on experience with coverage closure and writing SVA for IP/SOC. Good simulation debugging skills. Experience with Perforce or similar revision control environment. Experience with Python/TCL or any scripting knowledge is an added advantage. Job Responsibilities include - Understand Standard Specifications, create testplan for the product and create UVM based testbench architecture. Propose and enhance the UVM architecture with unique idea for verification. Be single point of contact with hands-on experience on all verification tasks - Testbench Creation - Testplan creation - Coverage closure - SVA - Release Perform peer review of testbench code for continuous quality. Own simulation debugs using DVE/Verdi, interact with Design Team and aid in debug and Verification closure. Periodically publish technical papers and/or file patents on the feature updates/innovation carried out. The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide. In addition, the candidate should have excellent oratory and written communication skills in English, should be a team player and possess good problem-solving skills and show high levels of initiative.