Static Timing Analysis (STA) Engineer Talent Corner Hr Services

5.0 - 10.0 years

15 - 25 Lacs

Bengaluru

Work from Office

Static Timing Analysis (STA) Engineer with hands-on experience in timing validation, analysis, and closure for complex SoC designs. Should have a strong background in STA flows using Tempus, along with a solid understanding of deep submicron nodes. Required Candidate profile Expertise in STA using Cadence Tempus, timing validation across multiple PVT corners, DMMMC flows, and timing closure at both block and full-chip levels, skills in TCL and Python are essential

Posted 5 days ago

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Sta consultant Zealogics.com

4.0 - 9.0 years

25 - 40 Lacs

Bengaluru

Work from Office

5+y in STA,tcl, python scripting Timing analysis,validation,debug Tempus DMMMC flow for STA STA setup,convergence, reviews,signoff for scan,function Endpoints,check timing reports,timing methodologies,noise, crosstalk,OCV Lower nodes 22nm,16nm,5nm

Posted 6 days ago

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Static Timing Analysis (STA) & Place and Route (PNR) Randstad India

10.0 - 14.0 years

0 Lacs

hyderabad, telangana

On-site

You will be responsible for leading Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems. Your main focus will be on achieving robust timing closure and optimal physical implementation with a keen eye on power, performance, and area optimization. It will be your duty to develop and enhance methodologies for STA and PNR that are specifically tailored to address the unique challenges faced by large, multi-interface, or mixed-signal subsystems. Your role will also involve driving automation and validation of timing and physical design data across subsystem boundaries. Furthermore, you will be required to mentor and provide guidance to junior engineers, nurturing their technical growth and promoting knowledge sharing within subsystem teams. Collaboration with various cross-functional teams will be essential to resolve design, timing, and physical implementation challenges that are specific to the integration of complex subsystems. Your qualifications should include a minimum of 10 years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, with expertise in advanced technology nodes such as 7nm or below. Proficiency in STA tools like Synopsys PrimeTime, Cadence Tempus, and PNR tools such as Synopsys ICC2, Cadence Innovus for application in large, multi-block, or hierarchical subsystems is required. A proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems is essential. Additionally, you should be skilled in scripting languages like Tcl, Perl, Python for automating STA and PNR flows across multiple subsystem blocks. A deep understanding of SoC design flows and experience in collaborating across frontend, physical design, and verification teams to integrate complex subsystems are crucial. Previous experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level would be advantageous. A background in high-speed interfaces or mixed-signal SoC subsystems is preferred for this role.,

Posted 2 weeks ago

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