3 Automated Synthesis Jobs

THE ROLE: As a Silicon Design Engineer in the AMD AECG ASIC TFM (Tools Flows Methodology) team, you will work with design experts to come up with the best implementation methodologies/flows and work on development and support of the BE flows. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Define and drive key Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Excellent physical design and timing background. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

THE ROLE: We are looking for an adaptive, self-motivative design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The Physical Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBLITIES: Handling SOC floorplanning/Partitioning,Die size estimation Experience on abutted and non-abutted designs Handling of Hierarchical designs (Subfcs),Block partitioning, block pin placement,Feedthrough punching, HFN implementation Planning clock Mesh/Tree at SOC/Sub System level Full SOC bump planning includingGPIO Bump Placement, Pad ring generation/GPIO placement,Hard IP bump placement,GPIO and PG RDL routing Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably ASIC designs. Knowledge on bump placement/critical IP placement. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

You will be part of Kinara, a Bay Area-based venture backed company, founded based on research conducted at Stanford University. Kinara's game-changing AI solutions aim to revolutionize what individuals and businesses can accomplish. Their Ara inference processors, combined with an innovative SDK, offer unparalleled deep learning performance at the edge. This enables the acceleration and optimization of real-time decision-making, emphasizing the importance of speed and power efficiency. By embedding high-performance AI into edge devices, Kinara contributes to creating a smarter, safer, and more enjoyable world. As the field of Edge AI is on the verge of a significant growth phase, Kinara is poised to play a pivotal role in this evolution. Your responsibilities will include the physical design of complex data path and control blocks, development of new techniques and flows for rapid hardware prototyping, creation of flows enabling detailed power estimation, collaboration with the design team to understand placement and recommend implementation options, as well as engagement with external teams to drive and deliver subsystems leading to chip tapeout. Preferred qualifications for this role include a BTech/MTech degree in EE/CS with at least 8 years of experience in Physical Design. You should possess extensive knowledge of Automated synthesis, Technology mapping, Place-and-Route, and Layout techniques, along with skills in Physical verification and quality checks such as LVS, DRC, IR drop, Clock tree synthesis, Power mesh design, and Signal integrity. Familiarity with the latest foundry nodes up to 7nm is desirable, as well as hands-on experience with various design aspects including Synthesis, Place-and-route, Full Chip STA, IO Planning, Floorplan, Power Mesh creation, Bump Planning, RDL Routing, and Low power design flows. Strong expertise in advanced digital design architectures and clocking structures is essential to manage timing and physical design constraints effectively. Furthermore, you should be able to collaborate with designers to analyze and explore physical implementation options for complex designs, possess basic knowledge of DFT techniques, and be familiar with industry-standard PnR, Synthesis, and TCL Scripting tools. Strong communication skills and the ability to work well in a team are also crucial. At Kinara, the work culture is centered around fostering innovation. The environment encourages professionals to tackle exciting challenges under the guidance of technology experts and mentors. The company values diverse perspectives and shared responsibilities, creating a collaborative and inclusive atmosphere where every individual's input is respected and appreciated. If you are passionate about making an impact and are eager to take on rewarding challenges, Kinara awaits your application eagerly. Join Kinara and be a part of a dynamic team that values innovation, collaboration, and personal growth. Your unique skills and experiences will contribute to shaping the future of AI solutions and advancing the field of Edge AI. Share your story with us, and let's work together to create a smarter, safer, and more enjoyable world.,