18 Ate Jobs

Test Engineer (Semiconductor) Role Summary: Develops and executes testing protocols to ensure semiconductor product quality and reliability. Key Responsibilities: Design test plans and procedures for ICs and systems. Use automated test equipment (ATE) for validation. Analyze test data and identify failure modes. Collaborate with design and manufacturing teams. Maintain test documentation and reports. Qualifications: Bachelors in Electrical or Electronics Engineering. Experience with ATE platforms (e.g., Teradyne, Advantest). Knowledge of statistical analysis and quality standards.

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for core Switching, Routing, and Wireless products. As a part of this team, you will contribute to designing networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations globally. Cisco Silicon One is a groundbreaking silicon architecture that allows customers to utilize top-of-the-line silicon in various network environments. Join us in shaping innovative solutions by working on the design, development, and testing of complex ASICs. In this role, you will collaborate with the team on Verilog RTL and scripted flow implementation of Hardware Design-for-Test (DFT) features to support ATE, in-system test, debug, and diagnostics requirements. You will also be involved in Verilog testbench implementation for verification tests and automation scripts to enhance implementation quality and efficiency. **Minimum Qualifications:** - Bachelor's or Master's Degree in Electrical or Computer Engineering with a minimum of 2 years of experience. - Proficiency in DFT, test, and silicon engineering trends. - Familiarity with JTAG protocols, Scan and BIST architectures, ATPG, and EDA tools. - Verification skills in System Verilog Logic Equivalency checking and Test-timing validation. **Preferred Qualifications:** - Understanding of VLSI circuit physical behaviors in silicon. - Knowledge of timing concepts and EDA tools usage. - Strong verbal communication skills and adaptability in a dynamic environment. - Proficiency in scripting/coding languages such as Tcl, Python, Perl, or C/C++. Cisco is committed to embracing diversity, fostering innovation, and driving digital transformation. With a focus on inclusive teamwork and a culture of creativity, we encourage individuality and support continuous learning and growth. At Cisco, we value accountability, boldness, and diversity of thought. Join us in our journey to create a future where technology drives positive change and equality for all.,

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for the core Switching, Routing, and Wireless products. We design networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations worldwide. Cisco Silicon One is a unique silicon architecture that allows customers to utilize top-of-the-line silicon in TOR switches, web-scale data centers, and across various networks with a unified routing and switching portfolio. Join our team and contribute to shaping Cisco's innovative solutions by participating in the design, development, and testing of cutting-edge ASICs. As a member of our team, you will be involved in the Verilog RTL and scripted flow implementation of Hardware Design-for-Test (DFT) features supporting ATE, in-system test, debug, and diagnostics requirements. Additionally, you will collaborate on Verilog testbench implementation for verification tests related to DFT features and use cases. Your role will also include contributing to automation scripts aimed at enhancing implementation quality and efficiency. **Minimum Qualifications:** - Bachelor's or Master's Degree in Electrical or Computer Engineering with a minimum of 2 years of experience - Knowledge of the latest trends in DFT, test, and silicon engineering - Proficiency in JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan - Familiarity with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime - Verification skills encompass System Verilog Logic Equivalency checking and validating the Test-timing of designs **Preferred Qualifications:** - Understanding of VLSI circuit physical behaviors in silicon, including electrical migration and temperature/voltage effects - Knowledge of basic timing concepts like setup and hold, metastability - Experience with EDA tools - Strong verbal communication skills and ability to excel in a dynamic environment - Proficiency in scripting/coding languages like Tcl, Python, Perl, or C/C++ Cisco is a diverse and inclusive environment where individuality is celebrated, and collaborative teamwork drives meaningful change for an inclusive future. Embracing digital transformation, we assist our customers in implementing digital changes in their businesses, showcasing our expertise as both a hardware and software company. Our innovative network solutions adapt, predict, learn, and protect, setting us apart as a company that defies traditional categorization. At Cisco, we value accountability, boldness, and diversity of thought. We foster a culture of innovation, creativity, and learning from failures, all while promoting equality for all individuals. Our inclusive environment encourages employees to be themselves, whether it's through unique personal styles or a passion for technology and positive change. Join us at Cisco, where your individuality and dedication to excellence are celebrated.,

You will be part of an Assembly & Test operations group, contributing to debugging test programs and yield enhancement activities. You will have the opportunity to engage in revenue improvement projects, interface with Customers, and troubleshoot device and test software as well as hardware at a first level. Your responsibilities will also include troubleshooting Electronics and Mechanical Equipment, as well as conducting breakdown maintenance. The ideal candidate should hold a Diploma in Electronics & Communications / Mechanical or an equivalent field. Direct experience in any ATE and IC Test Methodology is required, along with expertise in IC ATE test program debugging. Familiarity with measurement tools such as spectrum analyzers, oscilloscopes, or vector analyzers will be advantageous. You should be capable of working with minimal supervision, possess good project management and reporting skills, and be result-oriented with strong interpersonal skills for cross-functional collaboration. Excellent communication skills are essential for this role, along with the ability to multitask on multiple projects and perform effectively under pressure. Location: MM Nagar. To apply for this position, please email your resume to hr@natronix.net.,

As a member of the Common Hardware Group (CHG) at Cisco, you will be part of a team that delivers cutting-edge silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Our work involves designing networking hardware for Enterprises, Service Providers, Public Sector, and Non-Profit Organizations worldwide. Join us in shaping Cisco's groundbreaking solutions by participating in the design, development, and testing of advanced ASICs that are at the forefront of the industry. Your role will involve implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics requirements of the designs. You will collaborate with multi-functional teams to develop innovative DFT IP and play a crucial role in integrating testability features in the RTL. Working closely with design and PD teams, you will ensure the seamless integration and validation of test logic throughout all phases of implementation and post-silicon validation flows. Your team will contribute to the creation of innovative Hardware DFT and physical design aspects for new silicon device models, bare die, and stacked die. You will drive re-usable test and debug strategies while showcasing your ability to craft solutions and debug with minimal mentorship. To excel in this role, you are required to have a Bachelor's or Master's Degree in Electrical or Computer Engineering along with a minimum of 10 years of relevant experience. Your expertise should encompass knowledge of the latest trends in DFT, test, and silicon engineering. Proficiency in Jtag protocols, Scan and BIST architectures, ATPG, EDA tools, and verification skills like System Verilog Logic Equivalency checking will be essential. Preferred qualifications include experience in Verilog design, DFT CAD development, Test Static Timing Analysis, and Post-silicon validation using DFT patterns. Your background in developing custom DFT logic and IP integration, familiarity with functional verification, and scripting skills like Tcl, Python, or Perl will be advantageous. At Cisco, we value diversity, innovation, and collaboration. We empower our employees to bring their unique talents to work, driving positive change and powering an inclusive future for all. As a company that embraces digital transformation, we encourage creativity, innovation, and a culture that supports learning and growth. Join us at Cisco, where every individual is valued for their contributions, and together, we make a difference in the world of technology and networking.,

As a member of the Assembly & Test operations group, you will be involved in debugging test programs and implementing yield enhancement activities. You will have the opportunity to contribute to revenue improvement projects and engage in discussions with Customers regarding programs and products. Your responsibilities will also include troubleshooting of device and test software, as well as hardware at a first level. Additionally, you will be responsible for troubleshooting electronics and mechanical equipment, including breakdown maintenance. The ideal candidate for this position should have a Diploma in Electronics & Communications / Mechanical or equivalent field. Direct experience in any ATE and IC Test Methodology is required, along with experience in IC ATE test program debugging, which is highly desired. Familiarity with measurement tools such as spectrum analyzers, oscilloscopes, or vector analyzers is considered a strong advantage. The ability to work under minimal supervision, possess good project management and reporting skills, be bottom-line driven, have good interpersonal skills, and experience working in a cross-functional environment is essential. Strong communication skills are a must, along with the ability to multitask on multiple projects and perform well under pressure. This position is located in MM Nagar. If you meet the requirements mentioned above, please email your resume to hr@natronix.net.,

Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in Bangalore India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Who You Are You are an ASIC Design for Test Hardware Engineer with 10+ years of related work experience with a broad mix of technologies. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 10 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Experience working with Gate level simulation, debugging with VCS and other simulators. Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Strong verbal skills and ability to thrive in a multifaceted environment Scripting skills: Tcl, Python/Perl. Preferred Skills: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Test Static Timing Analysis Post silicon validation using DFT patterns. Why Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think were "old" (36 years strong) and only about hardware, but were also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you cant put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it). Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair Dont care. Tattoos Show off your ink. Like polka dots Thats cool. Pop culture geek Many of us are. Passion for technology and world changing Be you, with us!,

Role Overview : As the Functional Test Lead Engineer , you will play a key role in leading the design, development, and deployment of functional Automated Test Equipment (ATE). This role involves close collaboration with clients and internal teams to provide customized testing solutions for semiconductor and electronics products. You will manage ATE development projects from conception through production, troubleshooting technical issues, and deploying solutions globally. Key Responsibilities : ATE Architecture & Design : Architect, design, and prototype functional Automated Test Equipment (ATE) for semiconductor and electronics testing. Lead all phases of ATE development, including specification, design, prototyping, and production deployment. Client Engagement & Solutions Delivery : Work directly with customers to understand their requirements and deliver technical solutions in electronic measurement, test, and automation. Participate in client meetings, providing updates on technical progress and project management. Travel to global customer sites to deploy products and troubleshoot issues on the factory floor. Cross-functional Collaboration : Collaborate with internal teams including manufacturing, assembly, mechanical design, and software to ensure seamless product development and integration. Work across domains to ensure that all technical and project objectives are met. Required Skills : Proficiency in programming languages such as C/C++/Python/LabView/TestStand . Experience with embedded software platforms (e.g., TI, STM, NXP, ARM, Microchip) is a plus. Expertise in PCB circuit design, development, and debugging . Hands-on experience with bench equipment like oscilloscopes, power supplies, multimeters , etc. Knowledge of power electronics is a plus. Strong problem-solving and troubleshooting skills. Personality Traits : High-energy professional with a results-driven attitude. Process-oriented, with the ability to handle both high-level strategic thinking and detailed execution. Strong communication skills, able to effectively interact with clients and internal teams. Not afraid to embrace challenges or learn from failures. Enjoys interacting with people and can easily connect with others in a collaborative work environment.

1.Relay module & Terminal Block Assembly 2.Bottom Cover Assembly 3.PCB Initialization 4.Top Cover Assembly 5.Insulation Resistance 6.HV Testing 7.Functional Testing 8.Chemical Gluing 9.Meter Sealing 10.Laser Printing 11.OMB Assembly 12.Packing

As a Senior ATE Engineer You will be an active member of a scrum team that define and implement the ATE based SW test and quality improvement strategy for Smartest7 & SmarTest8 (Advantest V93K Tester Platform). Main tasks: Gain in-depth knowledge of the current Smartest test strategy, including its test coverage methods and reporting techniques. This involves assessing methodologies, enhancing coverage strategies, and applying efficient reporting practices to maintain accuracy and effectiveness. Be an integral part of the team working on Offline Result Emulation (ORE), deploying devices within the CI/CD pipeline, and monitoring Smartest performance. This involves ensuring smooth integration, optimizing deployment processes, and tracking system efficiency and reliability Scope of work mostly includes Offline simulation and Validation and may include Online testing/data collection and data analysis when required. The ability to comprehend test method logic and adjust it as required is essential. It involves analyzing the methodology, identifying optimization opportunities, modifying parameters, and validating changes to ensure accuracy and efficiency Define Test Plans and Test Procedures and executing test them offline/online mode during System test cycles. Validate new features of Smartest8 and provide necessary support for improvising, which includes exploratory testing and test method debugging. Working with team on various aspects of Advantest V93K systems & SMT8 application on Analog, RF and Digital platforms. Work with Product Owners to understand new features of Advantest 93K tester Platforms and develop test plans and test strategies. Work with subcontractors to implement test strategy & automate the tests. Required Skills: Bachelor or Master degree in Electronic/Electrical or Equivalent. Very Good Experience in ATE Domain (Advantest 93K). Prior experience of leading a team of ATE engineers would be an added advantage. Very good Knowledge of Advantest Tester Platforms, SMT7, SMT8 applications. Good Experience in test data analysis using tools like Exensio, Optimal+ etc. Good Experience in Test method debug & development would be an added advantage. Knowledge of programming languages (C++, Java, scripting) Excellent communication skills with Good English. Nice to have Work experience in different roles in an agile development environment (e.g. as developer, scrum master, PO, RTE, ALM) Proven knowledge of agile development approaches and/or frameworks (e.g. SAFe, Scrum of Scrum, Less, ) Experience in working in word-wide teams. Strong understanding of Semiconductor validation, testing on V93K test system. Good know-how of modern development platforms and tools (e.g. GIT, JIRA, ) Understanding of ATE business and latest technologies. Know-how of agile management tools like Jira, Azure DevOps. Good knowledge of RHEL (Linux) Knowledge of Java or C++ (intermediate) Make your mark in our exciting world at Siemens .This role, based in Bangalore , is an individual contributor position. You may be required to visit other locations within India and internationally. In return, you'll have the opportunity to work with teams shaping the future.

Role & responsibilities a. Guide / Mentor branches for ATE Business Development. b. Key Account Management. c. Manage Proposed Team for Timely submission of Technical Proposal & Commercial. d. Technically discuss with customer to finalise the scope. e. Negotiate & Finalise the deal. f. Interact with Execution and support team for fruitful completion of the project on time. g. Should have experience in ATE Business Development / Instrument Sales in EMS / EV Market. Preferred candidate profile BE/B.Tech graduates having 10+ Yrs of experience in ATE Business Development. Willing to travel Good Communication skills Should be go-getter and willing to meet customers and provide them with requisite technical solutions.

Role : Hardware Engineer Experience : 4 to 6 years Notice period : Immediate to 30 days Mode : Contract to Hire(C2H) Work Location : Bangalore Interview Mode : Face to Face(F2F) Mandatory Skills : Auto CAD Electrical ATE & Cable Design PBA Schematic Analysis Optional Skills : Interface Adaptor Circuit Design Hands on National Instruments tools If you are interested, please share your resume.

Role & responsibilities 3-5 years of LabVIEW development experience Aerospace ATE experience (recommended) Development of test software in LabVIEW, TestStand and Veristand (atleast 2 required) Atleast 2 projects executed as developer

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: DFT ATPG Engineer Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Minimum 4+ years of experience in ATPG and GLS • Good understanding of ATPG and DRC Analysis in ATPG • Handson in debugging low coverage • Handson in Simulation in no timing and timing with good debugging skills • Exposure to Silicon debug on ATE is an addon TekWissen Group is an equal opportunity employer supporting workforce diversity.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: Senior/lead DFT Engineer (MBIST) Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Minimum 8+ years of experience in Mbist Architecture, Insertion and Verification • Good understanding of Mentor Mbist Solution • Deliver Mbist patterns for ATE test • Support Mbist pattern failure on ATE TekWissen Group is an equal opportunity employer supporting workforce diversity.

Principal DFT Engineer Bangalore (Hybrid ) / Hyderabad (Hybrid ) Principal DFT Engineer Full Time \ Experienced Summary Join an ambitious, experienced team of silicon and distributed systems experts as a Design For Test engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solve key infrastructure challenges facing our customers. We are looking for talented, motivated candidates with experience building and deploying DFT flows for large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment. Roles & Responsibilities As a member of our team, you will work with multi-functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression. You will work with 3rd party IP vendors to integrate Memory BIST, scan, PHY I/O BIST, and other DFT logic into a streaming scan fabric with a sequential scan compressor/decompressor You will work with DFT Solutions Vendors to port those patterns at the top-level, to implement Memory BIST interface in high performance processor IP, and to implement high-speed I/O for the logic scan test You will work with Physical Designers to validate the DFT timing constraints You will work with RTL Designers to verify test design rules You will work with Test Engineers to bring up the patterns on the ATE Automated Test Equipment You will help develop and deploy DFT methodologies for our next generation products. Key Qualifications MSEE or equivalent experience 8-13+ years of experience in DFT or related domains You will have a solid knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation Possess excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools Have good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development Strong programming and scripting skills in Perl, Python or Tcl desired Exceptional written and oral and interpersonal skills with the curiosity to work on rare challenges Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Role & responsibilities We are looking 3 years of Exp in PCB Design (ATE Preferred) Knowledge about PCB Footprint creation Experience in DFM & DFA Analyses using CAM 350 Preferred candidate profile Diploma or any UG Degree. Both Male & Female can apply. Other Benefits PF & Medical Insurance Food Subsidy Interested share resume to vidya.ranganathan@pactroninc.in Mobile No: 9655603308

Hi, Warm Greetings! We are looking for Senior Manager - Software Engineer (with good in LabView & Teststand) and strong in Electrical or Electronics components, ATE, NI LabView, C embedded,etc ,. This Opportunity for a reputed MNC Organization based at Bangalore Location. Currently only looking for Female candidates. Description - External Seeking a suitable LabVIEW /TestStand software experience Engineer to join our SPD Bangalore Operations. Reporting to the Project Leader/GM Manager, the role demands for focusing on Single phase and three phase ATE's and PCBA BON design, Unit level test automation development for new products. Candidate should be able to bring, develop & communicate a strong knowledge of test applications and to be seen as an expert in this field by this Organization's customers & internally. Co-engineer, develop and implement the best test solutions for target customers, incorporating the Organization standards and Test policies. Improving the test coverages, work with relevant departments for analysis and come up with effective solutions, validate & prepare evaluation reports to release the test tools / equipments. Convert application knowledge & experience into added value for the business through writing application guides, bulletins, white papers, best practices and through the training of customers and internal Organization staff. Provide the technical support to enable Test Engineers to support for the manufacturing issues. Skills and Knowledge required: ATE Hardware Design and test automation coding design using Lab View /TestStand with suitable architecture. The Same thing should be validated in bench setup as well as ATE. Good knowledge in debugging, Failure Analysis, yield calculation and customer report generation. Primary responsibility of the role includes (but is not limited to): Understand the test spec and Development LabView and TestStand Application in Windows environment. Understanding the High-power Product functionality and derive Functional test spec for test ability and review, selection of suitable Instruments for ATE design, Knowledge in Electric and electronic component selection, basic wiring & Soldering, PCBA and Unit level test automation (Hipot, Functional and Load testing) Test Firmware / product firmware loading Engineering. Documentation: Understanding Functional Test spec, ATE / BON Bill of Material, Engineering Change Orders/Proposals, Test Plan, Test Procedures, Work Instruction and Electrical drawings review /creations. Database: Perforce, PDM, Jira and iTAC and MES Key Elements of the role: All types of PCBAs Functional BONs and single phase and three phases ATE development and idea on Measuring Instruments, Calibration and controls. Hands on experience in power instruments, programmable power supply using GPIB, RS232, RS485 and CAN Communication protocols. C, C++/ Python programming is knowledge added advantage. Experience and Requirements for the Role: 8-12 years of Experience in ATE/ BON, LabVIEW/ TestStand development for new product test automation and hands-on experience on Ni tools, ATE Bill of Material (BOM) and Engineering Change Orders (ECO) / Proposals, special equipment study and procurement. Design test bench setup using Three phase High voltage programmable equipments and handing with safety measures. Able to Test individual or stack PCBA group, unit sub-assembly and main unit level using bench test setup with power sources and multiple measuring instruments. Qualifications - External B.E/B.Tech/ M.Tech in ECE/EEE, Ni CLD / PMP trained or certified is preferable. Technical and commercial Tools: Hands on experience Ni LabVIEW, TestStand, C embedded And Perforce/SVN , ECAD, Oracle , PMP, PEP & Agile methodology. Communication: Good communication in English (read, write and speak) If you are interested, please share your cv to gowsalya@bvrpc.com Thanks & Regards, Gowsalya