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ASIC Engineer, Implementation

ASIC Engineer, Implementation

Meta

2 - 7 years

3 - 7 Lacs

Bengaluru

Posted:6 hours ago| Platform:

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Skills Required

Computer science Automation ASIC DFT Front end SOC Perl Floor planning Python Physical design

Work Mode

Work from Office

Job Type

Full Time

Job Description

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The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Metas computing efforts with capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Metas data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains.

ASIC Engineer, Implementation Responsibilities

Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them

Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities

Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures

Perform RTL Lint and work with the Designers to create waivers

Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults

Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC

Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC

Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks

Develop Power Intent Specification in UPF for the multi-Vdd designs

Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power)

Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback

Minimum Qualifications

Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

2+ years of experience in Design Integration and Front-End Implementation

Experience with Register-Transfer Level (RTL) Synthesis and design optimization for Power, Performance, Area

Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other Hardware Description Language (HDL)

Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues

Experience with Electronic Design Automation (EDA) tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. Experience with communicating across functional internal teams and vendors

Preferred Qualifications

Knowledge of Clock Domain Crossing, Reset Domain Crossing, Logic Error Correction (LEC)

Synthesis Background, Timing Constraints Development, Floorplanning and Static Timing Analysis (STA)

Experience Knowledge of Register-Transfer Level (RTL) coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, Static Random Access Memory (SRAM)

Experience with Power, Performance, Area Analysis and techniques for reducing power

Knowledge of Low power design. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools

Scripting and programming experience using Perl/Python, TCL, and Make

About Meta

Equal Employment Opportunity

Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .

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Menlo Park

Approximately 86,000 (2023) Employees

90 Jobs

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ASIC Engineer, Implementation