What Youll Do
Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.
Responsibilities
Looking for a Front-end Design ASIC Engineer.
Architectural work: in-depth understanding of the architecture, and identification of problems and solutions.
All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization.
Document and improve standard methodologies to make product successful.
Who You Are
Worked in architecture and definition of high-scale, high-performance ASICs.
Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing.
Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team.
Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion.
BS/MS and 5+/3+ years respectively of hands-on experience in large-scale, high-performance ASIC
BS/MS should be in EE/CS.
Minimum Qualifications
RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification)
Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS.
Gate-level understanding of RTL and Synthesis
Programming/scripting skills (C, C++, Perl)
Hardware Emulation Platforms and tools (such as EVE, Veloce)
Good written/verbal interpersonal skills and leadership skills.