15.0 - 20.0 years

0 Lacs

karnataka

On-site

As a highly motivated and innovative digital design engineer at Synopsys, you will play a crucial role in driving the innovations that shape the future in the Era of Pervasive Intelligence. Your expertise in ASIC design methodology and flows, particularly focusing on low power analysis and optimization, will be instrumental in empowering the creation of high-performance silicon chips and software content. With a proven track record in working with advanced nodes, especially at 5nm and below, you will be responsible for developing and driving digital design methodologies to achieve the lowest power consumption. Your strong background in both digital and physical design, coupled with your proficiency in developing timing constraints and UPF, will enable you to meet stringent power, timing, and area targets effectively. Collaborating closely with design teams and EDA tools teams, you will contribute to enhancing the power efficiency of high-performance silicon chips and driving innovation in low power design methodologies. Your role will involve conducting SAIF-based analysis, implementing best practices for low power design, and optimizing RTL designs to achieve optimal power consumption. To excel in this role, you will need to possess an MSEE or BSEE with over 20 years of digital design experience, including 15+ years of digital and/or physical design experience. Your expertise in low-power design techniques at RTL, proficiency in EDA tool flows, and excellent software and scripting skills (Perl, Tcl, Python) will be key to your success in this position. As part of the Digital Methodology Center of Excellence within Synopsys" IP team, you will collaborate with experienced engineers to develop cutting-edge digital design methodologies used across all IP development teams. Your organizational and communication skills, coupled with your ability to think and communicate at different levels of abstraction, will be essential in contributing to the successful implementation of advanced node technologies and industry-leading mixed-signal products. In addition to the challenging and rewarding work environment, Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.,

Posted 5 days ago

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Physical Verification Engineers Digicomm Semiconductor

5.0 - 9.0 years

0 Lacs

noida, uttar pradesh

On-site

As a Physical Verification Engineer at Digicomm Semiconductor Private Limited, you will be responsible for various crucial tasks to ensure the successful verification and validation of semiconductor designs. Your primary duties will include: Design Rule Checking (DRC): You will conduct DRC checks using industry-standard tools to identify any violations of manufacturing design rules. It will be essential for you to collaborate closely with layout designers to address and resolve any identified DRC issues effectively. Layout vs. Schematic (LVS) Verification: You will be tasked with performing LVS checks to verify the accurate alignment between the physical layout and the schematic design. Your role will involve ensuring there are no electrical connectivity discrepancies, thus guaranteeing the design's integrity and functionality. Electrical Rule Checking (ERC): Your responsibilities will also include verifying that the layout meets all electrical constraints and requirements, such as voltage and current limitations. By doing so, you will play a vital role in ensuring that the integrated circuit (IC) operates as intended without any electrical issues. Design for Manufacturing (DFM): Collaboration with design and manufacturing teams will be integral as you work to optimize the layout for the semiconductor fabrication process. You will need to address concerns related to lithography and process variations to enhance the manufacturability of the design. Process Technology Calibration: Your role will involve calibrating layout extraction tools and parameters to align with the specific process technology utilized for fabrication, ensuring accuracy and consistency in design implementation. Resolution Enhancement Techniques (RET): You will implement RET techniques to enhance the printability of layout patterns during the photolithography process, contributing to improved manufacturing outcomes. Fill Insertion: Inserting fill cells into the layout will be part of your responsibilities to enhance planarity and mitigate manufacturing-related issues such as wafer warping and stress, ensuring optimal design integrity. Multi-Patterning and Advanced Nodes: You will tackle challenges specific to advanced process nodes, including multi-patterning, coloring, and variations in the metal stack, ensuring proficiency in handling complex design requirements. Hotspot Analysis: Identifying and addressing potential hotspot areas that could lead to manufacturing defects or yield issues will be critical to ensuring the overall quality and reliability of the semiconductor design. Post-Processing Simulation: Conducting post-processing simulations to verify the layout's compatibility with the manufacturing process and to prevent the introduction of unwanted parasitic components will be essential to guaranteeing design accuracy. Process Integration Checks: Collaboration with process integration teams will be necessary to ensure a seamless integration of the design with the semiconductor fabrication process, optimizing overall design efficiency. Documentation: Maintaining detailed documentation of verification processes, methodologies, and results will be crucial to track progress, facilitate knowledge sharing, and ensure transparency in the verification process. Qualifications: - Bachelor's or Master's degree in Engineering (BTECH/MTECH) Experience: - Minimum of 5 years of relevant experience in the field of Physical Verification Engineering Location: - Bangalore/Noida Join us at Digicomm Semiconductor Private Limited and embark on an exciting career journey filled with growth opportunities and professional development.,

Posted 2 weeks ago

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