We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: we'll versed with timing signoff methodology and corner definitions Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring block/SS level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure PREFERRED EXPERIENCE: 3+ years of experience for timing closure of block/SS Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory. Good understanding of SDC construct ( clock generation , false path , multi cycle paths..) ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

THE ROLE: T he AI Models team is looking for exceptional machine learning scientists and engineers to explore and innovate on training and inference techniques for large language models (LLMs), large multimodal models (LMMs), image/video generation and other foundation models . You will be part of a world-class research and development team focussing on efficient and scalable pre-training, instruction tuning, alignment and optimization . As an early member of the team, you can help us shap e the direction and strategy to fulfill this important charter. THE PERSON: This role is for you if you are passionate about reading through the latest literature, coming up with novel ideas, and implementing those through high quality code to push the boundaries on scale and performance. The ideal candidate will have both theoretical expertise and hands-on experience with developing LLMs, LMMs, and/or diffusion models. We are looking for someone who is familiar with hyper-parameter tuning methods, data preprocessing & encoding techniques and distributed training approaches for large models. KEY RESPONSIBILITIES: Pre-train and post-train models over large GPU clusters while optimizing for various trade-offs . Improve upon the state-of-the- art in G enerat ive AI model architectures, data and training techniques. Accelerate the training and inference speed across AMD accelerators . Build agentic frameworks to solve various kinds of problems Publish your research at top-tier conferences, workshops and/ or through technical blogs. Engage with academia and open-source ML communities. Drive continuous improvement of infrastructure and development ecosystem. PREFERRED EXPERIENCE: Strong development and debugging skills in Python. Experience in deep learning frameworks ( like PyTorch or TensorFlow ) and distributed training tools (like DeepSpeed or Pytorch Distributed ) . Experience with fine-tuning methods (like RLHF & DPO) as well as parameter efficient techniques (like LoRA & DoRA). Solid understanding o f various types of transformer s and state space models . Strong publication record in top-tier conferences, workshops or journals. S olid communication and problem-solving skills. Passionate about learning new stuffs in this domain as well as innovating on top of it ACADEMIC CREDENTIALS: Advanced degree ( Master s or PhD) in machine learning, computer science, artificial intelligence, or a related field is expected. Exceptional Bachelor s degree candidates may also be considered . #LI-MK1 Benefits offered are described: AMD benefits at a glance .

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: The Role: We are looking for an experienced engineer to join the SOC Power Modeling team in the AMD Client Computing and Graphics group. This role involves collaboration with multiple engineering teams including SoC architecture definition, IP design, integration/physical design, verification, and platform architecture. Contributions have a direct impact on the power & performance of AMD’s Client products. The Person: The candidate should have SOC design process experience from front end to tapeout. The candidate will work closely with the SOC design teams on RTL and emulation-based power estimation, simulation and design data extraction. The candidate must be organized, self-motivated and able to work effectively on teams large and small across multiple sites. He or she must be able to prioritize assignments and drive them to completion. Good verbal and written communication skills are helpful for technical discussions with team members across the globe. Key Responsibilities: Work with front end RTL, DFT, Synthesis, and Physical design teams in the development of power intent (UPF) design at SoC level. Work with emulation team on power estimates during the pre-silicon design process using Power Artist/PTPX emulation environments and ensure power objectives and goals are met. Work with RTL and physical design teams to generate data on design impact from clock and power gating, device type mix and physical implementation options. Track IP power development through the design cycle ensuring it meets power budgets - leakage/dynamic at every milestone. Work with design verification in validating low power design features at SoC and IP level. Preferred Experience Experience with Synopsys EDA tools, particularly PtPx/Power Artist. Understanding of hardware emulation process, stimulus and EDA flows. Experience with Tcl and Python based scripting. Experience with UPF. Academic Credentials Master or Bachelor of Science degree in Electrical Engineering. 3+ years of experience. #LI-RR1 #LI-Hybrid Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SE NIOR SILICON DESIGN ENGINEER THE ROLE (SOC Verification Engineer: SOC NLP & Power Management): Work on SOC level verification activities, the person will be responsible for bringup of UPF simulation at SOC. Work with testbench team to bringup NLP (UPF) simulation, debug simulation issues. He will be responsible to coordinate with Design team for UPF delivery, work with design (IP, Subsystem, SOC) for quality UPF delivery and resolve issues. He should have good understanding of power architecture and UPF s He will be responsible to create TB collaterals for NLP simulation bringup. THE PERSON: Engineer with strong self-driving ability. Need excellent communication skills (both written and oral) Strong problem-solving skills, go to person for SOC testbench, Power management, UPF, C/C++ Coding, UVM coding, Testcase coding, checkers and assertions. KEY RESPONSIBILITIES: NLP Simulation bringup (Has responsibility of TB, Testcase, coordination between design and dv team) Power verification is key responsibility. Work with power architects to resolve issues seen in simulation. PREFERRED EXPERIENCE: Expertise in IP, Subsystem and SOC Verification with specialization in NLP Simulation. NLP Simulation is must requirement. Strong hands-on experience in different SOC Verification activities, NLP Simulation, Power verification, UVM, System Verilog, X86, C++, HW/SW co-verification, Scripting (phython) Test plan review, Debug/triage, Coverage, Strong Problem Solving, Automation and Debugging Skills, System bus protocol understanding including some of the common IPs like ACE, CHI, AXI, PCIe, DDR, memory controller etc. Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc. Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence. JIRA based project management is a plus. ACADEMIC CREDENTIALS: BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE 5-8 years of strong DV experience in NLP simulation, IP, Sub System & SOC Verification, Power management verification #LI-SR4 Benefits offered are described: AMD benefits at a glance .

SE NIOR SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, implement, and execute the Physical design and verification of processing subsystems IP, resulting in meeting the signoff criteria for tapeout. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and Implementation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. PREFERRED EXPERIENCE: 5+ Years of experience in relevant domain. Experienced with Blocklevel and Toplevel Physical implementation. Good understanding and hands-on experience in Lower node technologies. (7nm/5nm or below) Preferably working on Lowpower or processor designs. Proficient in Working with various EDA tools. Innovus, Fusion compiler/ICCompiler2, Primetime etc.., Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

We are looking for a dynamic, energetic Software Systems Design Engineer to join our growing team. As a key contributor to the success of AMD s products, you will be part of a leading team to drive and improve AMD s abilities to deliver the highest quality, industry-leading technologies to market. The Software Systems Design Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: As a Software Systems Design Engineer, you will deliver our next generation of products in the computer graphics industry 3D Gaming, Display Technologies, Compute, Virtual Reality, etc. In this high visibility position, your systems engineering expertise will be necessary to define products, develop solutions, assess root causes, and produce solution resolutions. As a senior member of the team, taking initiative in mentoring to achiev e the team s goal of on time delivery is expected. KEY RESPONSIBILITIES: Drive technical innovation to improve AMD s capabilities across product development and validation, including software tools and script development, technical and procedural methodology enhancement, and various internal and cross-functional initiatives . C onvert feature specifications into test cases (manual and automated) that will cover several types of testing - boundary, negative, functional, etc. W ork with multiple teams and tracking test execution to make sure all features are validated and optimized on time . W ork closely with supporting technical teams to validate new software features and new OS (Operating System) introduction . Le ad collaborative approaches with multiple teams . M entor others to achieve integrated projects . PREFERRED EXPERIENCE: Programming/scripting skills (e.g., C/C++, Perl, Ruby, Python) . Debug techniques and methodologies . Good knowledge and hands on experience in PC (Personal Computer) configurations (both Software and Hardware) with methods of Troubleshooting . Proven work on Windows and Linux operating systems . Knowledge of system architecture, technical debug, and validation strategies . Detailed oriented; ability to multitask through planning/organizing. Excellent Communication and Presentation skills . ACADEMIC CREDENTIALS: Bachelors or master s degree in electrical or computer engineering . Master s degree preferred.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SILICON DESIGN ENGINEER 2 THE ROLE: Play a critical role in shaping the next generation of AMD products, including CPUs, GPUs, and adaptive compute engines. Interface with large, globally distributed design teams to support complex and collaborative development efforts. Drive automation of Functional ECO methodologies targeting advanced technology nodes. Own the development and support of next-generation synthesis flows, ensuring scalability and efficiency across projects. Collaborate closely with EDA vendors to identify innovative solutions, resolve tool/methodology issues, and enhance flow capabilities. Contribute to the evolution of AMD’s design infrastructure by improving automation, performance, and methodology robustness. THE PERSON: You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites and timezones. You have an automation mindset with strong analytical and problem-solving skills, willingness to learn and ready to take on problems. KEY RESPONSIBILITIES: Responsible for developing and automating Functional ECO, Synthesize and PnR flows for various designs at advanced technology nodes. Script out utilities to automate different components of the implementation flow. Support design teams across global sites on various issues related to Front-End Synthesis flow targets. CAD flow and methodology development on advanced process nodes are preferred. PREFERRED EXPERIENCE: Hands on experience in Conformal ECO, Formal Eqv and Front-End Synthesis flows. Hands on experience in industry standard tools such as Conformal, DC, Fusion Compiler, FM,VCLP, ICC2 and Innovus . Hands on experience in any of PnR, STA, Formal Verification or RTL coding domains is a plus. CAD and automation mindset ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering with 3+Yrs of exp #LI-SR4 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SE NIOR SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, implement, and execute the Physical design and verification of processing subsystems IP, resulting in meeting the signoff criteria for tapeout. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and Implementation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. PREFERRED EXPERIENCE: 5+ Years of experience in relevant domain. Experienced with Blocklevel and Toplevel Physical implementation. Good understanding and hands-on experience in Lower node technologies. (7nm/5nm or below) Preferably working on Lowpower or processor designs. Proficient in Working with various EDA tools. Innovus, Fusion compiler/ICCompiler2, Primetime etc.., Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Post Silicon Validation THE ROLE: We are looking for a dynamic, energetic Lead / Senior Systems Design Engineer to join our growing team. As a key contributor to the success of AMD s product, you will be part of a leading team to drive and improve AMD s abilities to deliver the highest quality, industry leading technologies to market. The Systems Design Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. Specific role related asks would be: Develop Feature enablement plan & close on requirements with Architects , SOC Design team Must have lead team of Validation engineers , cross collaborate with Silicon DV & Deis FW , BIOS , Driver team Ensure the RAS features are gracefully enabled and validated againist the spec Active participation in the Debug of the issues reported during the course of validation. THE PERSON: As a Systems Design Engineer, you will drive balanced, scalable, and automated solutions. In this high visibility position, your software systems engineering expertise will be necessary towards p roduct development, definition, and root cause resolution. KEY RESPONSIBILITIES: Extensive experience in debug and validation roles involving OS, FW, Silicon, and HW issues. Proven record of working in the related fields such as high-end server products or Mid-end server products Expert knowledge of X86 architecture, memory, RAS and system management - BMC . Deeper understanding of the RAS fundamentals - MCA bank Architecture , Error checking , Error handling , Resets, Interrupts etc.. Deep understanding the system architecture and how each component will contribute to the overall RAS and other related functions. Understand architecture related to CPU, cache, memory, interrupt controller , etc Knowledgeable about various memory error types and how to handle these errors. In depth experience in specific fields such as memory and cache, PCI AER or storage RAS is a plus. Hands on with Error injection tools on various platforms. Knowledge about Advanced Platform Error Interface and how BIOS, FW firmware and OS work together. Should be well versed with using source control tools viz. JIRA Excellent communication skills to work with other engineers around the world. Driving technical innovation to improve AMD s capabilities across validation, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives Debugging issues found during the process, bring-up, validation, and production phases of SOC programs Working with multiple teams, and tracking test execution to make sure all features are validated and optimized on time Working closely with supporting technical teams Leading collaborative approach with multiple teams PREFERRED EXPERIENCE: Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc. Extensive experience with board/platform-level debugging, including delivery, sequencing, analysis, and optimization Extensive knowledge of system architecture, technical debug, and validation strategy Strong analytical/problem-solving skills and pronounced attention to details Must be a self-starter, and able to independently drive tasks to completion ACADEMIC CREDENTIALS: Bachelors or M asters degree in electrical or computer engineering Preferred experience 10 to 12 years with at least 5 years of relevant experience #LI-MK1 Benefits offered are described: AMD benefits at a glance .

The SoC and 3D-IC design construction CAD team provides automated environments for industry leading technologies and complex 3D stack products across the AMD portfolio The flows provide end-to-end automation for users across design planning, implementation, and analysis Experience with Verilog, clock and power distributions, high-performance bus implementation, and timing budgeting is preferred The role will be a part of a global team working in concert with project design teams from North America, China, and India You will work directly with the global CAD organization and project teams to understand the design requirements and deliver innovative solutions using EDA tools and custom in-house capabilities Individuals should have a strong silicon hardware design background and be proficient in software and scripting development 3D die-stack planning, integration, and routing Chip-to-chip and chip-to-package interface planning and implementation Bump/bond and TSV planning and layout Connectivity and DRC verification Design for signal integrity and thermal robustness Routing techniques for die-to-die communication protocols such as HBM and UCIe THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills, eager to learn, and ready to take on problems. KEY RESPONSIBILITIES: Work closely with CAD implementation members to deliver high quality tools and flows that meet all the key metrics of QoR: Manufacturability, Reliability, Timing, Area, and Performance. Regress methodology and develop capabilities to improve quality. Develop the strategy and key initiatives to ensure the CAD flows meet the future design needs and the most advances technologies. PREFERRED EXPERIENCE: 3-5 years experience in Silicon design or CAD/EDA development Understanding of EDA tools from Synopsys and Cadence Synopsys 3DIC Compiler experience is a plus Proficient in programming with Python and Linux Familiar in automating workflows in a distributed compute environment. Excellent communication skills (both written and oral). ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer Engineering/Electrical Engineering

Play a critical role in shaping the next generation of AMD products, including CPUs, GPUs, and adaptive compute engines. Interface with large, globally distributed design teams to support complex and collaborative development efforts. Drive automation of Functional ECO methodologies targeting advanced technology nodes. Own the development and support of next-generation synthesis flows, ensuring scalability and efficiency across projects. Collaborate closely with EDA vendors to identify innovative solutions, resolve tool/methodology issues, and enhance flow capabilities. Contribute to the evolution of AMD s design infrastructure by improving automation, performance, and methodology robustness. THE PERSON: You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites and timezones. You have an automation mindset with strong analytical and problem-solving skills, willingness to learn and ready to take on problems. KEY RESPONSIBILITIES: Responsible for developing and automating Functional ECO, Synthesize and PnR flows for various designs at advanced technology nodes. Script out utilities to automate different components of the implementation flow. Support design teams across global sites on various issues related to Front-End Synthesis flow targets. CAD flow and methodology development on advanced process nodes are preferred. PREFERRED EXPERIENCE: Hands on experience in Conformal ECO, Formal Eqv and Front-End Synthesis flows. Hands on experience in industry standard tools such as Conformal, DC, Fusion Compiler, FM,VCLP, ICC2 and Innovus . Hands on experience in any of PnR, STA, Formal Verification or RTL coding domains is a plus. CAD and automation mindset ACADEMIC CREDENTIALS: Bachelor s or M aster s degree in computer engineering/Electrical Engineering with 3+Yrs of exp

THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the Power Delivery convergence team , you will work closely with the architecture, physical design teams, package, board, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC electrical signoff convergence with physical design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Drive full chip IR/EM convergence on multiple ASICs across different technology nodes. Work closely with architecture, power management, package and floorplan team to come up with robust power delivery design. Work with RTL and PD team in coming up with the low power and UPF specification for the SoC. Work closely with CAD team to come up with new flows and methodologies in the power integrity domain. PREFERRED SKILLSET: 18+ years of professional experience in the industry with a proven track record of successfully delivering complex SoCs Sound knowledge of Power delivery and power integrity domains Hands on experience on industry standard tools especially Redhawk based power integrity analysis Should have lead IR/EM convergence on multiple full chip SoCs Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environment s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience . Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions . Expertise in Verilog, System Verilog, and Object-Oriented Programming Experience with UVM or similar Verification Methodology Requires strong Computer Architecture knowledge Comfortable in python / perl and editing / maintaining scripts Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out Experience with DRAM controllers, DDR Phys or DRAM Interface Protocols is a plus. Strong communication skills and the ability to work independently as we'll as in a cross-site team environment ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: Post Silicon Validation THE ROLE: We are looking for a dynamic, energetic Lead / Senior Systems Design Engineer to join our growing team. As a key contributor to the success of AMD’s product, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The Systems Design Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. Specific role related asks would be: Develop Feature enablement plan & close on requirements with Architects , SOC Design team Must have lead team of Validation engineers , cross collaborate with Silicon DV & Deis FW , BIOS , Driver team Ensure the RAS features are gracefully enabled and validated againist the spec Active participation in the Debug of the issues reported during the course of validation. THE PERSON: As a Systems Design Engineer, you will drive balanced, scalable, and automated solutions. In this high visibility position, your software systems engineering expertise will be necessary towards product development, definition, and root cause resolution. KEY RESPONSIBILITIES: Extensive experience in debug and validation roles involving OS, FW, Silicon, and HW issues. Proven record of working in the related fields such as high-end server products or Mid-end server products Expert knowledge of X86 architecture, memory, RAS and system management - BMC . Deeper understanding of the RAS fundamentals - MCA bank Architecture , Error checking , Error handling , Resets, Interrupts etc.. Deep understanding the system architecture and how each component will contribute to the overall RAS and other related functions. Understand architecture related to CPU, cache, memory, interrupt controller , etc… Knowledgeable about various memory error types and how to handle these errors. In depth experience in specific fields such as memory and cache, PCI AER or storage RAS is a plus. Hands on with Error injection tools on various platforms. Knowledge about Advanced Platform Error Interface and how BIOS, FW firmware and OS work together. Should be well versed with using source control tools viz. JIRA Excellent communication skills to work with other engineers around the world. Driving technical innovation to improve AMD’s capabilities across validation, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives Debugging issues found during the process, bring-up, validation, and production phases of SOC programs Working with multiple teams, and tracking test execution to make sure all features are validated and optimized on time Working closely with supporting technical teams Leading collaborative approach with multiple teams PREFERRED EXPERIENCE: Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc. Extensive experience with board/platform-level debugging, including delivery, sequencing, analysis, and optimization Extensive knowledge of system architecture, technical debug, and validation strategy Strong analytical/problem-solving skills and pronounced attention to details Must be a self-starter, and able to independently drive tasks to completion ACADEMIC CREDENTIALS: Bachelors or Masters degree in electrical or computer engineering Preferred experience 10 to 12 years with at least 5 years of relevant experience #LI-MK1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SILICON DESIGN ENGINEER 2 THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Will be working as a member of a cross geographic pre_silicon verification team to verify a next generation AI engine. Will be working with design, architecture team to verify micro-architecture and design across multiple platforms. Responsible for a comprehensive verification plan and drive the implementation of verification test cases from applications and other sources. Responsible for regression, verification infrastructure development Mentoring junior engineers PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools. Proficient in using UVM testbenches and working in Linux and Windows environments. Experience in specifying and developing the verification infrastructure for verifying CPU/DSP/Vector-Datapath designs. 3+ years of experience in the verification with experience of CPU/Video/DSP/vector processors, SIMD is a plus. Strong foundation in SoC architecture and verification of multi-core processors including SIMD, Vector processors, floating point, etc. is a plus. Expertise in Verilog/System Verilog, C/C++/SystemC, UVM, Scripting languages like Perl/Python, etc. Strong experience in HDL, verification, and general computational logic design/verification concepts Developing UVM based verification frameworks and testbenches, processes and flows. Strong analytical problem solving, and attention to detail. Excellent written and verbal communication skills. Excellent interpersonal skills, self-motivated ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RP1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: Senior Software Architect – GPU Kernel Optimization & Distributed AI Systems THE TEAM: Join AMD’s high-impact team at the heart of innovation in AI, ML, and high-performance computing (HPC). We’re a collaborative group of software architects and GPU engineers focused on pushing the boundaries of AI model performance across distributed, GPU-accelerated platforms. Our work drives the next generation of AMD’s AI software stack, enabling large-scale machine learning training and inference workloads in data centers and enterprise environments. THE ROLE: As a Senior Software Developer, you will develop both GPU kernel-level optimization and distributed software efforts for large-scale AI workloads. This is a technical leadership role with direct influence over critical software components in AMD’s AI stack. You’ll architect and implement optimized compute kernels, guide software teams through the full product lifecycle, and work closely with internal and external partners to deploy scalable, high-performance solutions. THE PERSON: We’re looking for a highly skilled, deep systems thinker who thrives in complex problem domains involving parallel computing, GPU architecture, and AI model execution. You are confident leading software architecture decisions and know how to translate business goals into robust, optimized software solutions. You’re just as comfortable writing performance-critical code as you are guiding agile development teams across product lifecycles. Ideal candidates have a strong balance of low-level programming, distributed systems knowledge, and leadership experience—paired with a passion for AI performance at scale. KEY RESPONSIBILITIES: GPU Kernel Optimization : Develop and optimize GPU kernels to accelerate inference and training of large machine learning models while ensuring numerical accuracy and runtime efficiency. Multi-GPU and Multi-Node Scaling: Architect and implement strategies for distributed training/inference across multi-GPU/multi-node environments using model/data parallelism techniques. Performance Profiling: Identify bottlenecks and performance limitations using profiling tools; propose and implement optimizations to improve hardware utilization. Parallel Computing : Design and implement multi-threaded and synchronized compute techniques for scalable execution on modern GPU architectures. Benchmarking & Testing: Build robust benchmarking and validation infrastructure to assess performance, reliability, and scalability of deployed software. Documentation & Best Practices: Produce technical documentation and share architectural patterns, code optimization tips, and reusable components. PREFERRED EXPERIENCE: Software Team Leadership Collaboration with customers and business units to define deliverables and roadmaps. Interfacing with executive leadership on program progress and strategic planning. Experience in production-level software deployment (e.g., upstreaming to open source, commercial rollouts). Software Architecture Deep experience with GPU kernel optimization in C++12/17/20 . Working knowledge of frameworks such as PyTorch, vLLM, Cutlass, Kokkos . Practical expertise in CPU/GPU architecture and system-level performance tuning. Proficiency in Python scripting and infrastructure automation. Application of software design patterns and industry-standard engineering practices. GPU & Low-Level Optimization Hands-on experience with CUDA and low-level GPU programming. Kernel optimization in assembly and tight loops for latency-sensitive code. Proficiency with performance profiling tools (Nsight, VTune, Perf, etc.). Experience with distributed computing strategies in AI environments (multi-GPU, NCCL, MPI). Strong debugging, problem-solving, and performance tuning skills in complex systems. ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, Computer Science, or a related technical field. Advanced degrees or published work in HPC, GPU computing, or AI systems is a plus. #LI-NR1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

We are hiring a ASIC Verification Engineer to help contribute to rapidly expanding and innovative chip designs in both 7nm and 5nm process technologies. We are developing cutting-edge domain specific processors for the IAAS and smart-switch markets that leverage the P4 programming language to provide software-defined features and scale but with hard-wired performance attributes. Applications include advanced PCIe, networking, storage, and security virtualization services for both the public and private cloud markets. THE ROLE: In this role, you will be responsible for defining test strategies and plans, developing test benches and test cases, and debugging designs helping with micro-architecture. You will participate in design verification methodology definition as we'll as contribute to design verification infrastructure that facilitates maximum re-use of components, improves productivity, and guarantees to the maximum extent possible, bug-free designs. Your work and skills will be leveraged across module-level, full chip, emulation, prototyping, silicon bring-up, manufacturing diagnostics, compilers, and shipping platform software. KEY RESPONSIBILITIES: With your solid knowledge and understanding of Computer Architecture you will be: Developing and executing test plans for Unit/IP/Subsystem/ SOC level verification System Verilog test bench development including stimulus, checkers, transactors/BFMs, assertions and cover points Identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills PREFERRED EXPERIENCE: Languages and tools: UVM, System Verilog, C or C++ System Verilog simulators and waveform debuggers Experience developing and executing test plans for Unit/IP/Subsystem/ SOC level verification Experience in System Verilog test bench development including stimulus, checkers, transactors/BFMs, assertions and cover points Experience identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy/DVE) Solid knowledge and understanding of Computer Architecture Excellent debugging and problem-solving skills ACADEMIC CREDENTIALS: BSEE or equivalent. MSEE preferred

Join AMD s high-impact team at the heart of innovation in AI, ML, and high-performance computing (HPC). We re a collaborative group of software architects and GPU engineers focused on pushing the boundaries of AI model performance across distributed, GPU-accelerated platforms. Our work drives the next generation of AMD s AI software stack, enabling large-scale machine learning training and inference workloads in data centers and enterprise environments. THE ROLE: As a Senior Software Developer, you will develop both GPU kernel-level optimization and distributed software efforts for large-scale AI workloads. This is a technical leadership role with direct influence over critical software components in AMD s AI stack. You ll architect and implement optimized compute kernels, guide software teams through the full product lifecycle, and work closely with internal and external partners to deploy scalable, high-performance solutions. THE PERSON: We re looking for a highly skilled, deep systems thinker who thrives in complex problem domains involving parallel computing, GPU architecture, and AI model execution. You are confident leading software architecture decisions and know how to translate business goals into robust, optimized software solutions. You re just as comfortable writing performance-critical code as you are guiding agile development teams across product lifecycles. Ideal candidates have a strong balance of low-level programming, distributed systems knowledge, and leadership experience paired with a passion for AI performance at scale. KEY RESPONSIBILITIES: GPU Kernel Optimization : Develop and optimize GPU kernels to accelerate inference and training of large machine learning models while ensuring numerical accuracy and runtime efficiency. Multi-GPU and Multi-Node Scaling: Architect and implement strategies for distributed training/inference across multi-GPU/multi-node environments using model/data parallelism techniques. Performance Profiling: Identify bottlenecks and performance limitations using profiling tools; propose and implement optimizations to improve hardware utilization. Parallel Computing : Design and implement multi-threaded and synchronized compute techniques for scalable execution on modern GPU architectures. Benchmarking & Testing: Build robust benchmarking and validation infrastructure to assess performance, reliability, and scalability of deployed software. Documentation & Best Practices: Produce technical documentation and share architectural patterns, code optimization tips, and reusable components. PREFERRED EXPERIENCE: Software Team Leadership Collaboration with customers and business units to define deliverables and roadmaps. Interfacing with executive leadership on program progress and strategic planning. Experience in production-level software deployment (e.g., upstreaming to open source, commercial rollouts). Software Architecture Deep experience with GPU kernel optimization in C++12/17/20 . Working knowledge of frameworks such as PyTorch, vLLM, Cutlass, Kokkos . Practical expertise in CPU/GPU architecture and system-level performance tuning. Proficiency in Python scripting and infrastructure automation. Application of software design patterns and industry-standard engineering practices. GPU & Low-Level Optimization Hands-on experience with CUDA and low-level GPU programming. Kernel optimization in assembly and tight loops for latency-sensitive code. Proficiency with performance profiling tools (Nsight, VTune, Perf, etc.). Experience with distributed computing strategies in AI environments (multi-GPU, NCCL, MPI). Strong debugging, problem-solving, and performance tuning skills in complex systems. ACADEMIC CREDENTIALS: Bachelor s or Master s degree in Computer Engineering, Electrical Engineering, Computer Science, or a related technical field. Advanced degrees or published work in HPC, GPU computing, or AI systems is a plus. #LI-NR1 Benefits offered are described: AMD benefits at a glance .

The right engineer will drive the success of power IP (Intellectual Property) and features in AMD (Advanced Micro Devices) products through leadership & coordination, resolution of technical dependencies, and achievement of schedule commits. This is a high-visibility and widely multi-functional role, spanning pre-silicon architecture to post-silicon implementation & product delivery. THE PERSON: Your curiosity will drive your learning and innovation to improve how we as a group, and an organization, can get better every day. Your peers will provide you a results-oriented and encouraging environment for your career growth, fueling your opportunity to be a part of Delighting Our Customers. KEY RESPONSIBILITIES: Power Management Firmware Engineer will play key role in ensuring AMD Embedded firmware (Power and Performance Management) addresses critical Embedded market segment (Networking, Storage, Automotive, Thin client) requirements performing the below: Contribute toqards AMD Embedded firmware development for PMFW, DXIO Collaborate with core firmware teams and ensuring Embedded requirements are addressed Coordinate debug of issues and drive them to closure. Work with Platform Firmware Organization (PFO) in conjunction with Embedded segment architects to meet product requirements Review key firmware requirement / enhancement inputs pertaining to focused Embedded markets Provide custom firmware design support for tier-1 customers by with identifying solution and providing design documents Design, develop, test, review features / releases pertaining to PMFW, DXIO firmware Provide low level design documents and user guides Pull together meetings, set up clear agendas and follow up on action items Assist customer support team in addressing any firmware related queries Proactively drive continuous improvement for post-silicon power and performance activities Must be a self-starter, and able to independently drive tasks to completion PREFERRED EXPERIENCE: 9-15 years experience in hands on firmware development. Strong with C language programming Good understanding and experience with BIOS, power management and PCIe Strong knowledge of ACPI , UEFI BIOS, AGESA knowledge is a big plus Good knowledge SoC power management CPU/Device power states, hot-plug etc Firmware development & release process understanding Prior experience working with firmware design & development OS/Drivers/Software stack understanding is a plus Product development or systems engineering background with hardware platforms and their software & firmware ecosystems Excellent verbal communication and written, presentation skills Excellent interpersonal, organizational, analytical, planning, and technical leadership skills Proven record of accomplishment in delivering large multi-functional product solutions Experience working in a fast-paced matrixed technical organization and multi-site environment ACADEMIC CREDENTIALS: bachelors or Masters degree in Computer or Electrical Engineering or equivalent

We are seeking an engineer to join our team that will thrive in a fast-paced work environment, using effective communication, problem-solving and prioritization skills. Individuals that are we'll organized, show great attention to detail, and employ critical thinking are we'll-suited for our team. THE PERSON: This AMD (Advanced Micro Devices) team is looking for a senior level person that can help guide the team, mentor upcoming developers, provide long range strategy, and is willing to jump in to help resolve issues quickly. You will be involved in all areas that impact the team including performance, automation, and development. The right candidate will be informed on the latest trends and become prepared to give consultative direction to senior management. KEY RESPONSIBILITIES: A powerful desire to learn new skills and understand new features as they are added Driver Tools roadmap for the BU including SW, HW and System tools across various OS /pre-OS environment Work across multiple teams - product management, marketing, customer front ending teams to understand the key tools requirements and drive them into the Tools roadmap for the BU Drive tools enablement with central engineering teams Proven record of accomplishment of working within and across groups. Identify optimization and automation opportunities and drive new tool needs within Engineering activities Drive the Tool development, validation and enablement aspects and ensure the Tools are maintained and upgraded appropriately Technical authority on quality of the tools Effective communication skills Responsible for exploring opportunities to improve product Work closely with other team members to understand design architecture and to propose solutions to improve and enhance products PREFERRED EXPERIENCE: Exposure to systems architecture Experience running, analyzing, and system benchmarks Solid programming skills in Python, C, or C++ Experience with Silicon development lifecycle, both pre-silicon and post-silicon ACADEMIC CREDENTIALS: Bachelor s or Master s in Electrical Engineer, Computer Engineering, Computer Science, or a closely related field