Identify , recruit & develop new channel partners to meet business goals . Liaison between AMD and its partners, ensuring seamless communication and alignment on business objectives. Engage in Joint Business Planning with OEMs and Channel Partners to increase AMD SoW Conduct weekly meetings with partners sales team to review performance against quarterly goals . Identify opportunities and develop action plan for future. Build and deploy customer engagement plan which includes direct customer engagement and working with channel partners. Identify potential SMB customers & drive AMD adoption to meet or exceed our SMB growth targets. Position and sell AMD technology in new customers and new market segments. Understand products, customer needs, competitors, industry issues, and trends, then continually refine the message, positioning, product demos, and sales tools to meet business objective . Build and manage the sales pipeline . Train & enable partners sales & presales on AMD products & solutions . Execute AMD Partner Programs ,aligning it with overall business goals. Education / Experience requirement : Bachelor s or master s degree . MBA desired 10 to 12 yrs of IT hardware Sales experience

THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities: Physical Design Implementation: Translate complex CDNA and RDNA graphics IP RTL designs into optimized physical layouts. Utilize industry-leading EDA tools for synthesis, place-and-route (PnR), and physical verification processes to take the design thru mock-taepout Performance Optimization: Focus on power, performance, and area (PPA) optimization to meet the stringent requirements of high-performance graphics and compute products. Collaborate with architecture and front-end design teams to align RTL design with physical constraints and objectives. Verification and Timing Closure: Conduct static timing analysis (STA) to ensure robust timing closure and sign-off for graphics IP. Implement and verify design rule checks (DRC), layout versus schematic checks (LVS), and power grid analysis tailored to CDNA and RDNA requirements. Collaboration and Communication: Work closely with cross-functional teams, including architects, RTL designers, and verification engineers to ensure seamless integration and functionality of graphics IP cores. Provide feedback and suggest improvements to design methodologies and processes to push the technology envelope further. Documentation and Reporting: Maintain comprehensive design documentation, methodologies, and updates. Prepare detailed reports on design progress, performance metrics, and any technical challenges encountered. PREFERRED EXPERIENCE: Domain Expertise: Experience with working on complex design and optimizing for performance, power, and area. Technical Proficiency: Proven track record in RTL synthesis, place-and-route (PnR), and static timing analysis (STA) for complex IP cores. Proficiency with industry-leading EDA tools, such as Synopsys Design Compiler, Cadence Innovus, and timing analysis tools like PrimeTime. Experience with low-power design methodologies and techniques for high-performance graphics IP. Design and Verification: Successful completion of full-chip sign-off, including design rule checks (DRC) and layout versus schematic (LVS) checks. Strong skills in signal integrity analysis, including crosstalk and IR drop evaluations. Process Technology: Experience working with advanced semiconductor process nodes (e.g., 7nm, 5nm, or below). Knowledge of process-related challenges and optimization techniques for graphics applications. Scripting and Automation: Proficiency in scripting languages such as Perl, Python, or TCL to automate design flows and improve efficiency. Experience developing and maintaining scripts for design rule checks and optimization processes. Problem-Solving and Innovation: Demonstrated ability to solve complex design challenges using innovative approaches. A track record of contributing to the improvement of design techniques and methodologies in a graphics-focused engineering team. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #

SILICON DESIGN ENGINEER 2 THE ROLE: As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence . THE PERSON: Software engineer with strong C++, C Python skills along with GPU architecture and ISA exposure for GEMM kernel development KEY RESPONSIBILITIES: GPU ISA understanding and kernel development for MI instinct customising architecture for optimal kernel Performance modelunderstanding for debug and optimisation Emu/Sim expertise for kernel customising and debug Familiarity in Driver based emu setup run and debug PREFERRED EXPERIENCE: 2+ experience in GPU performance ACADEMIC CREDENTIALS: Bachelor s or M aster s degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance .

SE NIOR SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, SOC design, design quality checks and design automation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Design of Subsystems with integration of AMD and other 3rd party IPs Understand clocking, reset and soc top level topology changes to make connectivity as per the topology across IPs Collaborate with architects, Verification engineers, and Physical design Engineers to understand the new features to be designed and integrated in SoC Understand SOC power domain requirements(power architecture) to write UPFs Perform quality checks: Lint, CDC, Low Power checks, Timing constraints, LEC for complex digital designs Identify areas for automation and create solutions to improve productivity and quality, continuously improve the automation process by exploring new tools and technologies PREFERRED EXPERIENCE: Proficient in Verilog and System Verilog with good understanding of RTL design flows and process Detailed understanding of SoC design flows Experience with version control system such as perforce Verilog lint(Spyglass) and simulation tools (VCS) Good understanding and hands-on experience in UPF, CDC, RDC, Timing constraints, LEC and other design quality check concepts Good with Scripting languages such as Python, Perl, Makefile, TCL and unix shell Automating workflows in a distributed compute environment Experience with embedded processors, data fabric architectures (NoC) and standard protocols such APB/AXI Stream and AXI MM Ability to work with multi-level functional teams across various geographies Strong problem-solving and analytical skills ACADEMIC CREDENTIALS: B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering with Digital Systems/VLSI as major. #LI-SR5 Benefits offered are described: AMD benefits at a glance .

LOCATION: Bangalore WHAT YOU LL BE DOING: Candidate has opportunitites to work on functional and performance analysis of various enterprise tools and also research on LLVM compiler support for various cutting edde modern programming lanugages. If good in LLVM compiler tool chain and compiler internals, has potential opportunity to get hands on modern programming standards. Candidate can leverage opportunity to understand end to end flow of compiler development Opportunity to contribute and claim to the success of AMD CPU compilers working with the world class compiler engineers and performance engineers in AMD and in opensource communities Daily responsibilities may include root cause analysis of compiler issues, communicating with the compiler engineers, participating in team meetings, downstreaming LLVM community code, research on compiler functions across AOCC and competition etc.. By end of the COOP candidate is expected to have gained a good knowledge and experience on end to end work flow of compiler development and release. A good knowledge on functional support of LLVM, GCC and intel compilers. Potential to gain confidence on compiler engineering with hands on to compiler code base KEY QUALIFICATIONS: Compiler design, LLVM/GCC compiler tool chain, Strong in C++. Any knowledge in devops tools and process including gtihup, gerrit and Jenkins is an added advantage Do not include specific years of experience, or use the word REQUIRED (use preferred or desired). WHAT WOULD SET YOU APART: Good problem solving skills. Appetite to learn and explore the unknown WHO WE RE LOOKING FOR: Bachelors in computer engineering from a reputed institute with good communication skills who is looking for COOP in his/her final year #LI-SG1 Benefits offered are described: AMD benefits at a glance .

MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Computing and Graphics group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. RTL/Integration- Design Engineer The Person: If you have experience developing RTL for IP or subsystems and understand architectural specifications, this role is for you. You will be responsible for IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. Key Responsibilities: Design of IP and subsystems with integration of AMD and other 3rd party IPs Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up Lead a subsystem development team of 4 to 5 members. Preferred Experience: 5-7 years full-time experience in IP hardware design Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs Verilog lint tools (Spyglass) and verilog simulation tools (VCS) Clock domain crossing (CDC) tools Detailed understanding of SoC design flows Understanding of IP/SS/SoC Power Management(PM) techniques Power Gating, Clock Gating Experience with embedded processors and data fabric architectures (NoC) Outstanding interaction skills while communicating both written and verbally Ability to work with multi-level functional teams across various geographies Outstanding problem-solving and analytical skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS1 Benefits offered are described: AMD benefits at a glance .

MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the Design of new and existing features for AMD s IPs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the IP and/or new features to be designed Build design documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to design the new features and QA checks Documentation of the Micro Architecture Specification Work with the verification team to review the test plan and make sure all features are covered Debug test failures to determine the root cause; work with Verification and firmware engineers to resolve design defects PREFERRED EXPERIENCE: Proficient in IP level ASIC RTL Design Proficient in debugging firmware and RTL code using simulation tools Proficient in working with Linux and Windows environment s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the SystemVerilog language and UVM based verification Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to DDR, SERDES or other multimedia solutions . ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

The right engineer will drive the success of power IP (Intellectual Property) and features in AMD (Advanced Micro Devices) products through leadership & coordination, resolution of technical dependencies, and achievement of schedule commits. This is a high-visibility and widely multi-functional role, spanning pre-silicon architecture to post-silicon implementation & product delivery. THE PERSON: Your curiosity will drive your learning and innovation to improve how we as a group, and an organization, can get better every day. Your peers will provide you a results-oriented and encouraging environment for your career growth, fueling your opportunity to be a part of Delighting Our Customers. KEY RESPONSIBILITIES: Looking for security engineer with strong system and software security fundamentals. Candidate should have : Strong knowledge in cryptography fundamentals, including asymmetric and symmetric cryptography: All modes of symmetric algorithm AES Asymmetric algorithm like RSA, ECC Knowledge for Digital signature and Digital certificate X.509 format. Understanding of system design and security component in it. Understanding of different phases of Secure Development lifecycle of a solution Experience in threat modeling techniques, preferably with hands-on experience using Microsofts threat modeling tool and STRIDE methodology Experience in Root of Trust-based security development and trusted OS development Strong analytical skills required Secure communication protocols like TLS, SSH C language (Essential), C++ and RUST (desired). Must be a self-starter, and able to independently drive tasks to completion PREFERRED EXPERIENCE: Product development or systems engineering background with hardware platforms and their software & firmware ecosystems Excellent verbal communication and written, presentation skills Excellent interpersonal, organizational, analytical, planning, and technical leadership skills Proven record of accomplishment in delivering large multi-functional product solutions Experience working in a fast-paced matrixed technical organization and multi-site environment Product or program management ACADEMIC CREDENTIALS: bachelors or Masters degree in Computer or Electrical Engineering or equivalent

We are seeking an engineer to join our team that will thrive in a fast-paced work environment, using effective communication , problem-solving and prioritization skills. Individuals that are we'll organized, show great attention to detail, and employ critical thinking are we'll-suited for our team. THE PERSON : Th is AMD (Advanced Micro Devices) team is looking for a senior level person that can help guide the team, mentor up coming developers, provide long range strategy, and is willing to jump in to help resolve issues quickly. You will be involved in all areas that impact the team including performance , automation, and dev elo p ment . The right candidate will be informed on the latest trends and become prepared to give consultative direction to senior management. KEY RESPONSIBILITIES: A powerful desire to learn new skills and understand new features as they are added Proven record of accomplishment of working within and across groups. Effective communication skills Responsible for exploring opportunities to improve product Work closely with other team members to understand design architecture and to propose solutions to improve and enhance products 14+ years of solid experience in C programming we'll versed with data structures, ability to write maintainable code Excellent in operating system internals, synchronization primitives, memory management and multi-threaded applications Exposure to writing code that scales for multi-threads/CPU cores, compiler optimization in GCC or others. we'll versed with development of Kernel modules/drivers, debugging, analyzing core dumps in Linux (preferably embedded), RTOS/FreeRTOS Hands on with different performance analysis techniques Experience in platform security (At hardware level, Trusted execution environment) Exposure to coding in assembly and having good understand of processor architecture (ARM/X86/Xtensa) is desirable Demonstrated strong verbal and written communication skills, and interpersonal and teamwork skills Strong analytical and problem-solving skills PREFERRED EXPERIENCE: Exposure to systems architecture Experience running, analyzing, and system benchmarks Solid programming skills in Python, C, or C++ ACADEMIC CREDENTIALS: Bachelor s or Master s in Electrical Engineer, Computer Engineering, Computer Science, or a closely related field

Performance modelling and evaluation of ACAP workloads to eliminate bottlenecks as early as possible and guide the architecture of future generation devices. This is a challenging role in the FPGA Silicon Architecture Group in AECG business unit of AMD in Hyderabad. ABOUT THE TEAM: AECG group in AMD designs cutting edge FPGAs and Adaptable SOCs consisting of processor subsystems and associated peripherals, programmable fabric, memory controllers, I/O interfaces and interconnect. KEY RESPONSIBILITIES: Modelling and simulation of workload dataflow networks and clock accurate SOC components. Performance analysis and identification of bottlenecks Quick prototyping, long-term design decisions, and exploring novel architectures Enhancement of the existing tools and knowledgebase Collaborating with architects in the development of next generation devices Collaborating with customer facing teams to identify scope of optimization for future market scenarios Breaking down system level designs into simpler dataflow models and identify bottlenecks, capture memory and communication overheads Knowledge sharing with teammates through thorough documentation PREFERRED EXPERIENCE: Preferred experience in SOC architecture OR Performance analysis. Strong background in Computer architecture, Hardware performance metrics and bottlenecks. Experienced in modelling and simulation of hardware. Experience in performance profiling, creating experiments to address various use-cases and doing design space exploration. Good to have experience of creation of designs for ACAP devices or HLS. Good communication skills ACADEMIC CREDENTIALS: bachelors or Masters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

We are looking for a technical leader to join and lead the SOC Power Modeling team in the AMD Client Computing and Graphics group. This role involves collaboration with many engineering teams including SoC architecture definition, IP design, integration/physical design, verification, platform architecture, software, and firmware. Contributions have a direct impact on the power & performance of AMD s Client products. The Person: The candidate should have strong SOC design process experience from front end to tapeout. The candidate will lead a team working closely with the SOC design teams on RTL and emulation-based power estimation, simulation and design flow extraction. The candidate must be organized, self-motivated and able to work effectively on teams large and small across multiple sites. He or she must be able to prioritize assignments and drive them to completion. Strong verbal and written communication skills are essential for driving technical discussions to successful and actionable outcomes. Key Responsibilities: Team leader for Hyderabad based power modeling group, work with management to define department objectives and growth plans. Make recommendations to improve processes or procedures as appropriate. Implement changes to engineering processes based on new technologies or industry standards. Work with department management on recruiting, hiring, training, and team e valuations . Work with frontend RTL, DFT, Synthesis, and Physical design teams in the development of power intent (UPF) design at SoC level. Lead team with power estimates during the pre-silicon design process using Power Artist/PTPX emulation environments and ensure power objectives and goals are met. Work with RTL and physical design teams to scientifically assess and manage tradeoffs with impacts of power management options such as, but not limited to clock and power gating, device type mix and physical implementation options. Track IP power development through the design cycle ensuring it meets power budgets - leakage/dynamic at every milestone. Improve power design flows in areas of power modeling, clock power analysis, structural power validation, IP power intent. Work with design verification in validating low power design features at SoC and IP level. Preferred Experience Extensive experience with Synopsys EDA tools, particularly PtPx/Power Artist. Detailed understanding of hardware emulation process, stimulus and EDA flow data extraction. Ability to define data reporting and requirements needs using EDA flows, Tcl and Python based scripting. Ability to work independently and lead a world-wide team. Excellent communication skills, written and verbal skills Academic Credentials PhD or Master of Science degree in Electrical Engineering, Computer architecture, or Computer Science. 10+ years of experience.

As a member of the NBIO IP Physical aware group, you will help bring to life cutting-edge designs. As a member of the Physical aware person, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve best quality and PPA for complex IPs THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: STA, timing analysis. Interface timing analysis, generate ECO. Primetime expert. Synthesis of Complex IPs, constraint developement. Develop feedback to RTL team for physically driven microarchirtecture changes, Manage data for shared design across multiple projects. corrdintation with multiple SOC for complex IPs PREFERRED EXPERIENCE: Understanding of STA and synthesis design cycle. 5+ experience in physical design and syntheis domain ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

We are looking for an adaptive, self-motivative Synthesis/PD/STA engineer to join our growing team. As a key contributor, you will be part of a team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The Physical Design Engineering team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and physical design in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects for the new features to be implemented in layout End-to-end RTL to GDS implementation of complex IPs and supporting the SOC customers Working with RTL team to resolve timing and congestion issues Build and develop methodology to converge multiple PNR blocks from RTL to GDS Analyze design metrics and make implementation choices to optimize PPA PREFERRED EXPERIENCE: ASIC design flow and direct experience with ASIC design in sub-7nm technology nodes Circuit timing/STA, and practical experience with Prime Time or equivalent tools Low power digital design and analysis Expertise in synthesis and physical design flows Modern SOC tools including Synopsys Fusion compiler, Primetime and Redhawk TCL, Perl, Python scripting Strong verbal and written communication skills Ability to organize and present complex technical information Fluent in working with Linux environment Mimimum 6 years of industry experience ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

The Unified Memory Controller team is looking for a passionate and self-motivatived design engineer to join our growing team. As a key contributor , you will be part of a leading team that develops industry-leading memory controllers used across a wide variety of AMD products. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Microarchitectural design and RTL implementation of IP features Analyze RTL design for power optimization and timing optimization Collaborate with Design verification team to execute on design features/timing/synthesis Participate in design specification and RTL code reviews PREFERRED EXPERIENCE: Digital design engineering experience with 4+ Years. Excellent knowledge of verilog, system verilog, C and a scripting language; experience with python, perl and tcl Proficient in debugging RTL code using simulation tools Knowledge of clockign architectures, synchronization, and CDC methodology DDR, memory controller design experience is preferred Strong understanding of computer architecture ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environment s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience . Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions . ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

MTS SOFTWARE SYSTEM DESIGN ENGINEER THE ROLE: The right engineer will drive the success of power IP (Intellectual Property) and features in AMD (Advanced Micro Devices) products through leadership & coordination, resolution of technical dependencies, and achievement of schedule commits. This is a high-visibility and widely multi-functional role, spanning pre-silicon architecture to post-silicon implementation & product delivery. THE PERSON: Your curiosity will drive your learning and innovation to improve how we as a group, and an organization, can get better every day. Your peers will provide you a results-oriented and encouraging environment for your career growth, fueling your opportunity to be a part of Delighting Our Customers. KEY RESPONSIBILITIES: API Testing, API Test Development, Performance benchmarking & analysis, automation Owner of the quality of compiler libraries. Define test strategies and release test plans for AMD optimized Compiler Libraries. Define/develop/execute regression test cases and track the results to closure Automate manual test cases and integrate them into the regression test suites. Drive innovation in production software environments Combine advanced software engineering skills with a drive to explore novel approaches to solve important problems in heterogeneous computing at the large scales Evaluate and review of existing processes and continuously strive to optimize the workflow PREFERRED EXPERIENCE: 9 - 12 years of experience in API testing and developing test cases for embedded software Experience of programming/scripting with Perl, Python, Shell, TCL/TK Good understanding of build ecosystem especially CMake. Make build systems is a plus Understanding of C/C++ programming languages is a must Working experience on GTest, PyTest is preferred. Hands on experience in building/developing test automation frameworks Knowledge of Windows and Linux environments Experience with software development process and tools such as debuggers and source code control systems a plus Good debugging, analytical and communication skills ACADEMIC CREDENTIALS: Bachelor s or Masters degree in Computer or Electrical Engineering or equivalent #LI-NS2 Benefits offered are described: AMD benefits at a glance .

MTS SILICON DESIGN ENGINEER Responsibilities: Feature based performance Testplan, Test writing, performance verification, Arch model closure, RTL Performance verification closure Shader development expertise Driver workload, benchmarks, micros, GEMM Kernel development and debug Strong SV/C-C++ based BFM development skills. Memory modelling. Strong networking and colloboration with Arch, design, SOC, Post Silicon, Workload , Driver teams Requirements: BS +12 years or MS +10 years work experience preferred. Strong Graphics Architecture understanding Excellent Graphics IP level debug expertise for compute and 3D Strong Block and Graphics top level feaature wise perf analysis and debug skills Compute , Cache , HBM memory Bandwidth test developement and performance closure Feature wise shader and content development skills Scripting Python/Perl Garpahics Arch modelling content run and closure Familiarity with latency pipeline and performance bottle neck analysis Strong memory/cross-bar data path understanding and bandwidth rollup Post silicon bug recreation/debug methodologies/ SOC level understanding and IP modelling Good understanding of memory hierarchy, caches, address translations schemes. Good understanding of general dram technologies and address translation schemes Familiarity with Computer organization/architecture. Strong analytical/problem solving skills and pronounced attention to details. Must be a self-starter, and able to independently drive tasks to completion. Good teamwork and communications skills are required Strong leadership and innovation mind bent Flair for Graphics market development and innovations #LI-NS1 Benefits offered are described: AMD benefits at a glance .

SOFTWARE DEVELOPMENT ENGINEER 2 THE ROLE: AMD is looking for a specialized software engineer who is passionate about improving the performance of key applications and benchmarks . You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Work with AMD s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develop new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partners PREFERRED EXPERIENCE: Strong object-oriented programming background, C/C++ preferred Ability to write high quality code with a keen attention to detail Experience with modern concurrent programming and threading APIs Experience with Windows, Linux and/or Android operating system development Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus Effective communication and problem-solving skills ACADEMIC CREDENTIALS: Bachelor s or Masters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent Benefits offered are described: AMD benefits at a glance .

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Front-end implementation from RTL to netlist, including RTL Lint, CDC/RDC analysis, timing constraints, Power Analysis, STA for Multi-Media IPs Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. Analyze the inter-block timing and come up with IO budgets for the various partition blocks. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Perform RTL Lint and work with the Designers. Analyze RTL CDC/RDC and work with Designer for potential Clock and Reset Design Domain crossing issues. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities. Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power). Implementing Functional ECOs using Conformal and writing manual Ecos. Work with Architects, RTL Designers and SOC teams for efficient IP Quality. PREFERRED EXPERIENCE: 5 to 10 years of experience in Front-end implementation from RTL to netlist Familiarity with Power Analysis Experience/Background on Computing/Graphics is a benefit ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

As a Software Functional Safety Architect , part of AMD Functional Safety team, you will be directly impacting the certification of key AMD products, targeting critical AMD growth markets such as digital cockpit and autonomous driving. Your task will be to provide technical leadership for the product line safety function and for its customers. You will perform this in close cooperation with different functional owners within AMD. This challenging role will not only require extensive embedded software architecture and design skills but also a thorough understanding of system safety standards within the automotive and industrial markets. We are seeking a software functional safety architect to join our team that will thrive in a fast-paced work environment, using effective communication, problem-solving and prioritization skills. Individuals that are we'll organized, show great attention to detail, and employ critical thinking are we'll-suited for our team. THE PERSON: This AMD (Advanced Micro Devices) team is looking for a senior level person that can help guide the team, mentor upcoming developers, provide long range strategy, and is willing to jump in to help resolve issues quickly. You are open minded, positive and detail focused as you will be involved in all areas that impact the team including performance, automation, and development. KEY RESPONSIBILITIES: Implementing functional safety engineering tasks as defined in the product safety plan. Supporting in defining and streamlining the functional safety processes according to IEC 61508 and ISO 26262. Performing end to end traceability analysis from requirements to verification and validation tests. Performing software safety analysis using FMEA, FTA and other applicable techniques. Performing software tools analysis according to IEC 61508 and ISO 26262. Participating in national and international functional safety working groups. A powerful desire to learn new skills and understand new features. Effective written and verbal communication skills. Good people skills. Initiative-taking approach to improve AMD s software quality and safety compliance. REQUIRED EXPERIENCE: 13+ years of Experience with firmware, device drivers and embedded software design, development, and testing. Experience with the ISO 26262 or IEC 61508 functional safety standards focusing on software. Experience with requirements management process with tools like JAMA, DOORS or similar. REQUIRED QUALIFICATION: Bachelor s or masters in Computer/Electrical /Electronic Engineering or a closely related field. Individual Functional safety certification (IEC 61508 or ISO 26262) obtained through TUV or Exida. Proficiency in low level C and Assembly programming (x86 or ARM or other RISC architecture). Proficiency in Embedded Linux or another Real Time Operating System (RTOS). PREFERRED QUALIFICATION: Exposure to software quality standards Automotive SPICE or CMMI. Exposure to AUTOSAR framework. Exposure to automotive cybersecurity (ISO 21434) or industrial cybersecurity standards (IEC 62443) focusing on software. Exposure to the concept of usage of Artificial Intelligence / Machine Learning in safety critical systems.