Staff / Sr. Staff Verification Engineer, Interface IP

As an experienced ASIC Digital Verification Engineer at Synopsys, your role is crucial in ensuring the highest quality in digital design. Your deep understanding of verification methodologies and proficiency in using advanced tools allow you to independently tackle complex challenges and deliver innovative solutions. You are detail-oriented, possess a strong analytical mindset, and effectively communicate with stakeholders. Your extensive experience enables you to mentor and lead junior engineers, showcasing your expertise in the field. You will be responsible for designing and implementing verification environments, creating detailed test plans, developing verification IP and testbenches, collaborating with design teams, performing functional coverage analysis, and mentoring junior engineers. Your contributions will impact the delivery of high-quality ASIC designs, enhance verification processes, drive innovation, and improve Synopsys" IP offerings. - Design and implement verification environments for Interface IP protocols - Create and execute detailed test plans for complex ASIC designs - Develop and maintain verification IP and testbenches using SystemVerilog and UVM - Collaborate with design teams to identify and fix bugs - Perform functional coverage analysis and drive coverage closure - Stay updated with the latest verification methodologies and tools - Mentor and guide junior verification engineers - Extensive experience in ASIC digital verification, particularly with Interface IP protocols - Proficiency in SystemVerilog and UVM methodologies - Strong understanding of digital design and verification concepts - Experience with simulation tools like VCS, ModelSim, or similar - Excellent problem-solving skills and attention to detail,