Staff / Sr. Staff Verification Engineer, Interface IP

Synopsys

3 - 6 years

3 - 6 Lacs

bengaluru karnataka india

Posted:1 day ago| Platform: Foundit logo

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Skills Required

asic digital design chip design modelsim uvm hardware verification

Work Mode

On-site

Job Type

Full Time

Job Description

Designing and implementing verification environments to ensure the correctness of Interface IP protocols.
Creating and executing detailed test plans to verify complex ASIC designs.
Developing and maintaining verification IP and testbenches using SystemVerilog and UVM.
Collaborating with design and architecture teams to identify and fix bugs.
Performing functional coverage analysis and driving coverage closure.
Staying current with the latest verification methodologies and tools to continually improve processes.
Mentoring and guiding junior verification engineers in best practices and methodologies.

The Impact You Will Have:

Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.
Enhancing the robustness and efficiency of our verification processes and methodologies.
Contributing to the successful launch of Interface IP products, impacting various industries.
Driving innovation and excellence within the verification team.
Improving the overall performance and functionality of Synopsys IP offerings.
Fostering a culture of continuous improvement and technical excellence.

What You ll Need:

Extensive experience in ASIC digital verification, specifically with Interface IP protocols.
Proficiency in SystemVerilog and UVM methodologies.
Strong understanding of digital design and verification concepts.
Experience with simulation tools such as VCS, ModelSim, or similar.
Excellent problem-solving skills and attention to detail.

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