Staff / Sr. Staff Verification Engineer, Interface IP

Role Overview: At Synopsys, you will be driving innovations that shape the way we live and connect, leading in chip design, verification, and IP integration to empower the creation of high-performance silicon chips and software content. As an experienced ASIC Digital Verification Engineer, you will play a crucial role in ensuring the highest quality in digital design, leveraging your expertise in verification methodologies and advanced tools to deliver innovative solutions. Key Responsibilities: - Design and implement verification environments for Interface IP protocols - Create and execute detailed test plans for complex ASIC designs - Develop and maintain verification IP and testbenches using SystemVerilog and UVM - Collaborate with design and architecture teams to identify and fix bugs - Perform functional coverage analysis and drive coverage closure - Stay updated with the latest verification methodologies and tools - Mentor and guide junior verification engineers in best practices Qualifications Required: - Extensive experience in ASIC digital verification, particularly with Interface IP protocols - Proficiency in SystemVerilog and UVM methodologies - Strong understanding of digital design and verification concepts - Experience with simulation tools such as VCS, ModelSim, or similar - Excellent problem-solving skills and attention to detail,