Design & Verification Engineer

Siemens

2 - 7 years

7 - 11 Lacs

noida

Posted:1 month ago| Platform:

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Skills Required

vmm system verilog sv uvm pcie soc verification c++ usb simulation digital design vhdl rtl design axi fpga rtl coding debugging coloring ahb asic asic verification python eda software testing ovm rtl verilog asic design ethernet ddr flash

Work Mode

Work from Office

Job Type

Full Time

Job Description

We make real what matters.

This is your role.

Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques.
You will specify, implement, test and enhance these verification components for a wide range of end user applications.
You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger.
You will get along with TMEs and Field AEs or directly with customers to deploy or resolve customer issues.

We dont need superheroes, just super minds.

You're an Electronics Engineer (B.Tech/ M.Tech) or related field from a reputed institute
You've got phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well.
You've sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc.
You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc.
You are a great teammate, resilient and sincere, Enjoy learning new things and build knowledge base in new area.

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