928 Fpga Jobs

Skills/Experience: Extensive experience in IP/SOC Verification. Must be proficient in System Verilog and UVM. Must have hands-on experience in the verification of the IP protocols such as PCIe/DDR/USB/Ethernet/CXL/HDMI/MIPI/DSI/CS/GLS/CPU Verification or any other high-speed protocols. Experience with scripting language (Python, Perl, TCL etc.) Experience in assembly language or C is a plus. Ability to create testbenches from scratch and own the complete verification including coverage of the subsystem/chip level. Strong debugging capabilities. Experience (years) : 3 - 12 Years Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Experience with STA using Primetime and PTPX required Proficient in constraint generation. Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl scripting is required Strong problem solving and ASIC development/debugging skills. Experience with CPU micro-architecture and their critical path. Low power implementation techniques experience. High speed CPU implementation. Place and route tool experience. Constraint management tool and Verilog coding experience Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

We make real what matters. This is your role. Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will get along with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We dont need superheroes, just super minds. You're an Electronics Engineer (B.Tech/ M.Tech) or related field from a reputed institute You've got phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well. You've sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. You are a great teammate, resilient and sincere, Enjoy learning new things and build knowledge base in new area.

We require an accomplished Photonics Optical Alignment Engineering Lead to join our team. The Photonics Optical Alignment Engineering Lead will develop and implement optical alignment procedures for silicon photonics devices such as silicon dies, laser diodes, optical modulators, and photodiodes. The engineer / lead will collaborate closely with the global SME and R&D team to create new products and will be responsible for optimizing the optical alignment process to achieve high yields and high dependability. In addition, the engineer / lead will be required to work autonomously and assist the development of the process till mass production. Key Responsibilities: Lead optical alignment efforts for free space and fiber optics, ensuring precision and accuracy in alignment processes. Develop and implement alignment procedures and protocols to meet project requirements and deadlines. Mentor and guide junior engineers in optical alignment techniques and best practices. Collaborate with cross-functional teams, including design, manufacturing, and quality assurance, to optimize alignment processes and outcomes. Troubleshoot and resolve alignment-related issues as they arise during execution. Stay current with industry trends and advancements in optical alignment technology, incorporating relevant innovations into project workflows. Qualifications : Bachelor's degree in Optical Engineering, Physics, or a related field. Masters degree is preferable. 7 years of experience in optical alignment engineering, with demonstrated expertise in either in-house developed system or off-shelf optical alignment systems. At least 5 years of experience in practicing statistical engineering and familiarity in application of statistical engineering for parametric optimization activities. Proven leadership skills with experience in managing and mentoring junior engineers. Strong analytical and problem solving abilities, with a keen attention to detail. Excellent communication and interpersonal skills with the ability to collaborate effectively with cross functional teams. Ability to thrive in a fast paced, dynamic work environment, managing multiple projects simultaneously.

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing]. We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. Desired experience: 2-5 years of experience in Physical design, STA. Solid understanding industry standard tools for physical implementation [ Genus, Innovus, FC, PT, Tempus, Voltas and redhawk]. Solid grip from floorplan to PRO and timing signoff along with understanding of IR drop and physical verification aspect. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker Tempus Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

This Position reports to: Team Lead Product Engineer Your role and responsibilities In this role, you will have the opportunity to execute technical assignments. Each day, you will deliver technical solutions as per agreed timeline and standards using established solutions. You will also showcase your expertise by supporting the development of technical expertise solutions and services. This role is contributing to Motion Drive Product business division based in Peenya, Bangalore, India You will be mainly accountable for: Coordinating and planning daily design and testing activities according to the project scope and schedule Solving technical challenges by using your own solid competence in AC drive technologies Actively seeking new and innovative technical concepts to differentiate our products from competitors and increasing customer value Mentoring and leading younger designers by your own example and experience Working in close collaboration : - with project and product managers giving your valuable feedback and ideas to the management, various design and competence teams to ensure best possible solutions for technical challenges, with our key component suppliers and partners Qualifications for the role Qualification : BE Electrical and Electronics or EEE , M-tech Power electronics or Control system or Drives 5+ years experience in the development of 3- phase AC drives (VFD drives) or corresponding experience Good understanding of Power electronics, mechanics, thermal management, FPGA, embedded software, PWM motor control, design for manufacturing and quality Expertise in modern 3-phase AC drives (VFD Drives) converter topologies, and power electronics components, with strong simulation skills and a forward-looking view on drives technology trends." Experienced in high-power electronics with strong fundamentals in SMPS, DC-DC converters, and embedded systems(FPGA, MCU). Skilled in hardware design, simulations, thermal/mechanical considerations, and cross-disciplinary collaboration using modern tools and test equipment." Mastery of electromagnetic compatibility and functional safety requirements, Product extensive validation, reliability testing and product application testing.

Job Area: Engineering Group, Engineering Group Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing]. We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. Desired experience: 2 years of experience in Physical design, STA. Solid understanding industry standard tools for physical implementation [ Genus, Innovus, FC, PT, Tempus, Voltas and redhawk]. Solid grip from floorplan to PRO and timing signoff along with understanding of IR drop and physical verification aspect. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker Tempus Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language .

Skills/Experience: Strong design fundamentals with hands-on experience in front-end design flows Hands-on experience in design of micro-architecture blocks, RTL coding, block-level verification. Hands-on experience in Linting, CDC analysis of reports, identify ways to fix the violations Hands-on experience in SoC/IP integration Excellent understanding of SoC components like processors, memories, peripherals, IOs Good understanding of at-least one of the protocols like UFS/PCIe/SAS/SATA/USB Experience of working with ARM or ARC (Synopsys) processors/sub-systems Experience of UPF flow, updating constraints Ability to work independently, ramp-up quickly and work with verification/validation teams for front-end flows Good experience in PERL/TCL scripting Good verbal and written communication skills are required. Education Qualification: BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field

Work Profile : - Work on development of custom Analog circuit boards for applications related to RF, interfaces etc. - Implement new features and bug fixes - Verify analog/mixed-signal integrated circuits - Develop test cases to verify new features and bug fixes - Review and update the user manuals for software tools. - Supporting digital modelling of analog circuits for mixed-signal verification - Creating design specifications and circuit schematics - Work both independently and in a team environment, with the opportunity to provide technical leadership to other members of the engineering team - Create and/or modify specification documents detailing system design and enhancements to meet marketing requirements - Collaborate with others in the creation of technical reports, whitepapers, and user documentation Requisites : - EE/EEE/ECE graduate, undergraduate degree from reputed Tier 1 or Tier 2 colleges . - Strong knowledge of analog integrated circuit design fundamentals - Proven experience taking designs from concept to production - Experience in analog/mixed-signal IC design & verification - Understanding of BJT, CMOS and Op-Amp technologies. - Good understanding of analog/mixed-signal design flows (Cadence, Synopsys) - Transistor and system level simulation skills - Discrete time and continuous time signal processing skills - Strong lab and silicon validation skills - Verilog based digital design and test bench development, is a plus - Strong communication skills, both written and verbal.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: FPGA Design. Experience: 3-5 Years.

Role & responsibilities : 1. High speed Digital Architecture Design ( Microcontroller, Microprocessor and FPGA based architecture) with 1553 interface. 2.System Design with Xilinx/Alteral / Actel FPGA devices with relevant tools and IPs. 3.Board level testing and system debugging. 4.Should be aware of DACs, ADCs, FPGAs, Buffers, Transceivers, LDOs, POL,1553 chips, Microprocessors, Microcontrollers, etc. 5.Mixed signal design architecture. 6.Protocols knowledge like USB, GBE, PCle, RS232, etc. 7.Generation of BOMs. 8.Generation of Electrical Interface Document ( EID). 9.Experience in Derating analyis. 10.Generate the reliability factor for the systems. 11.Experiance in FMECA, FMEA, worst case analysis. Interested candidate kindly share me your updated CV at jeevabvr@gmail.com

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

He / she is responsible for proactively identifying, evaluating, and mitigating risks associated with the obsolescence of components within a company s products or systems. Their role is critical in ensuring the sustained operability and support of existing products while strategically managing the transition to updated components or designs as needed. Also shall be aware about how to read PCB ckt & suggest alternative Qualifications, Experience & skills Mandatory skills & competencies: Education: BE Electrical / Electronics Experience Level: 3+ Years Software Tools: . SAP, OM Tool IHS matrix, Silicon expert Good to have Skills & competencies Checking of obsolescence cases in the hardware (evaluation of PDN and PCN in product context, coordination with OM manager) Understanding and evaluating hardware circuits and the use of affected components Creation of hardware requirements for specification changes Design of hardware circuits (microcontroller, FPGA, analog and digital technology) Review of analog and digital circuit parts, understanding of the connections Re-engineering of existing hardware circuit parts and devices Integration of hardware modules in and for new hardware platforms under Consideration of layout and EMC issues Experience in handling ECAD tools hardware and obsolescence management (e.g. CR8000 with DS-CR, OM tooling, e.g. Silicon Expert)

RTL Design and FPGA prototyping experience of ASIC - IP & SoC Integration - To Integrate various IPs into Sub-System/SoC. - Handle all integration flows (IP/SoC) including clocking, resets, interrupts, Bus interfaces, Fuses, Security, Address Map etc. - To run all QA checks including compile, lint, CDC, Synth Elab, CLP, Register File generation at IP/SoC - To develop glue logic at IP/SoC for various requirements including IPC, Address decoding, top-level control/status registers, security etc - Involve in initiatives being pursed in IP/SoC Integration including automation.

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s chip design team. As a member of DFT team you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug. You will play a key role in silicon bring-up, workload execution and validation. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Proficiency in C and Python for validation and automation Hands on experiencec in Writing/ maintaining test programs and automation scripts using C and Python Experience in chip bring-up /debug Experience in chip-level throttling issues including power, thermal, and frequency-related behavior Knowledge on Analyzing trace data/logs and on-chip debug outputs for failure root cause Should be able to Interpret Verilog RTL to support functional and performance debug Collaborate with RTL, firmware, validation, and DFT teams for end-to-end issue resolution Strong understanding of chip boot flows and bring-up sequences Familiarity with assembly-level debugging on RISC/V, ARM, or other architectures Ability to read and debug Verilog RTL code In depth understanding of chip internals, including resets, clocking, and register programming Preferred technical and professional experience Experience in post-silicon validation, emulation or pre-silicon environments Exposure to firmware-hardware interactions Knowledge of debug infrastructure and on-chip monitoring tools Familiarity with version control tools like Git

Lead the Architecture, Design and development of processor MMU (Memory management unit) for high- performance IBM Systems. - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the MMU feature enhancements. - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of experience in the memory management/ memory controller delivery leadership. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. Good understanding of industry trends & advances in - 8 to 15 years of relevant experience - At least 1 generation of experience in the memory management/ memory controller delivery leadership. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. Good understanding of industry trends & advances in architecting high bandwidth memory solutions.

End-to-end design and development of features for IBM high performance Mainframe and POWER processors and ASICs. Develop the feature, present the proposed architecture in the High level design discussions Estimate the overall effort to develop the feature Develop micro-architecture, Design RTL, Collaborate with the Verification, Physical design, FW teams to develop the feature Pre Silicon: Signoff the Design that meets all the functional, area and timing goals Post Silicon: Bringup and Validate the hardware functionality Required education Bachelor's Degree Required technical and professional expertise 1 to 3 years of professional experience Experience with HDLs- VHDL/ Verilog Understand and Design Power efficient logic. Drive design closure including test plan reviews and verification coverage Understand of logic synthesis, Physical Design concepts, Timing, and constraints Prior experience in and knowledge in one or more areas : I2C, I3C, SPI, AXI, AHB, APB, boot, security, debug and trace, OTP ROM, clocks and resets, silicon bringup

We are seeking a highly experienced Staff Design Engineer with 10+ years of expertise in RTL design and digital signal processing for our Bengaluru location (max 30 days notice period). The ideal candidate will be responsible for designing, developing, and integrating custom DSP components such as filters, FFTs, and control logic for Aevas advanced 4-D Lidar processing chip across ASIC and FPGA platforms. The role involves creating micro-architecture specifications, writing and validating SystemVerilog RTL code, and ensuring designs meet stringent performance, low-power, and robustness requirements. The engineer will collaborate with architects, verification, and system software teams to achieve SoC functional and performance goals. Strong proficiency in DSP architectures, AMBA protocols, and RTL coding is required, along with proven ability to deliver high-quality designs. Preferred skills include Matlab/NumPy/C/C++, high-speed SerDes, FPGA-based validation, and post-silicon bring-up.

We are seeking a highly experienced Staff Design Engineer with 10+ years of expertise in RTL design and digital signal processing for our Bengaluru location (max 30 days notice period). The ideal candidate will be responsible for designing, developing, and integrating custom DSP components such as filters, FFTs, and control logic for Aevas advanced 4-D Lidar processing chip across ASIC and FPGA platforms. The role involves creating micro-architecture specifications, writing and validating SystemVerilog RTL code, and ensuring designs meet stringent performance, low-power, and robustness requirements. The engineer will collaborate with architects, verification, and system software teams to achieve SoC functional and performance goals. Strong proficiency in DSP architectures, AMBA protocols, and RTL coding is required, along with proven ability to deliver high-quality designs. Preferred skills include Matlab/NumPy/C/C++, high-speed SerDes, FPGA-based validation, and post-silicon bring-up.

We are seeking a highly experienced Staff Design Engineer with 10+ years of expertise in RTL design and digital signal processing for our Bengaluru location (max 30 days notice period). The ideal candidate will be responsible for designing, developing, and integrating custom DSP components such as filters, FFTs, and control logic for Aevas advanced 4-D Lidar processing chip across ASIC and FPGA platforms. The role involves creating micro-architecture specifications, writing and validating SystemVerilog RTL code, and ensuring designs meet stringent performance, low-power, and robustness requirements. The engineer will collaborate with architects, verification, and system software teams to achieve SoC functional and performance goals. Strong proficiency in DSP architectures, AMBA protocols, and RTL coding is required, along with proven ability to deliver high-quality designs. Preferred skills include Matlab /NumPy/C/C++, high-speed SerDes, FPGA-based validation, and post-silicon bring-up. Skills : - Staff Design Engineer, RTL Design, System Verilog, ASIC, FPGA, DSP, Signal Processing, AMBA, Micro-Architecture, SoC, Low-Power Design, Verification, Matlab, NumPy, C, C++, LPDDR, SerDes, MIPI, Ethernet, FPGA Validation, Post-Silicon, Diagnostics Firmware

Preferred candidate profile & Job Description Bachelors /Masters degree in Engineering Engineering Students / Freshers with strong passion in Electronics and Semiconductor domain are also considered Relevant experience of 0-3 yrs in any of the mentioned domain - Design/Verification/ Implementation is an advantage but not mandatory Will be working on cutting-edge Wireless Technology team. Strong fundamentals in core areas: Microarchitecture, Computer Arithmetic, Circuit Design, Process Technology

RGreetings!!!!! We are looking for a Engineer / Sr. Engineer _ FPGA Design _ Bangalore location for a leading Indian multinational in Electronics System Design & Manufacturing. Job Responsibilities: High-speed digital architecture design (FPGA based) FPGA design using Xilinx devices & tools (Vivado/ISE) Implementing DSP algorithms on FPGA Hands-on with protocols: JESD204, LVDS, Aurora, UART, SPI, I2C Perform Static Timing Analysis (STA), synthesis, placement, routing & floorplanning Apply design constraints for timing closure Develop test benches for verification & validation Collaborate with cross-functional teams for new product development Requirements: 4 to 8 years of FPGA design experience Strong in RTL to FPGA implementation & onboard testing Experience in DSP algorithm-to-hardware conversion Good knowledge of verification, validation & debugging methods If your interested share with the below details to uma@bvrpc.com Please share your updated resume along with: Current CTC Expected CTC Notice Period

Role: FPGA Engineer Experience: 46 years Location: Yelahanka Qualification: BE/MTech in Electronics Key Responsibilities: Design and implement high-speed digital architectures using FPGA (Xilinx/Altera/Actel). RTL coding in VHDL/Verilog , synthesis, P&R, STA, and timing closure. Develop testbenches, perform verification & validation, and onboard testing. Work on communication protocols: 1553, USB, PCIe, Ethernet, RS232, I2C, SPI, etc. Collaborate with cross-functional teams for new product development. Debug FPGA systems using industry-standard tools. What Were Looking For: Strong experience in FPGA design flow – from RTL to hardware validation. Hands-on expertise in algorithm-to-hardware implementation. Problem-solving, debugging skills, and ability to work independently. Interested candidates can share your resume with srinidhi@bvrpc.com

System Design & Architecture : Lead architectural planning and design of software systems prioritizing scalability, reliability, and maintainability. Development & Coding : Write clean, efficient, and well-documented code. Implement robust testing, including unit and integration tests. Project Leadership : Drive projects from concept to delivery. Break down tasks, estimate effort, track milestones, and manage technical risk in collaboration with PMs and stakeholders.

Role Description Share point developer with good experience in Pages and Workflow. Excellent Communication skills. Offshore resource who specializes in Sharepoint (i.e. Pages, workflow) development, etc.). 5-6 yrs of experience.