422 Asic Verification Jobs

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Board Design. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: Mechanical Part design. Experience: 3-5 Years.

Job Description: SOC Verification engineers with 3+ years of experience Knowledge of ARM architecture, CPU fundamentals & Cache coherency Experience with C/C++, assembly, and scripting languages. Familiarity with low-power design and verification Develop CDV UVM verification environments at system level Verify CPU connectivity to IP blocks Develop SoC test plans and test cases and track metrics including code and functional covera Job Requirement: Bachelors or Masters in EE/CS or related field 3+ years of SoC in ASIC/FPGA verification experience Proficiency in SV and UVM Experience with simulation, emulation, and formal verification Strong debugging and problem-solving skills Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As a Design Verification Engineer, you will be responsible for verifying complex SoC designs, working closely with design teams to ensure robust and high-quality products. You will employ advanced verification methodologies and tools to identify and resolve issues, ensuring that our SoC designs meet industry standards and customer requirements. Responsibilities: 1. Develop and execute comprehensive test plans to verify the functionality of SoC designs. 2. Create and maintain verification environments using advanced verification techniques, such as UVM, SystemVerilog, and assertion-based methodologies. 3. Collaborate with design teams to debug and resolve functional issues in RTL and gate-level simulations. 4. Ensure thorough verification coverage by analyzing and improving functional coverage metrics. 5. Perform regression testing to ensure consistent performance and reliability across design iterations. 6. Work closely with architects and designers to understand design specifications and refine verification strategies. 7. Develop reusable verification components and ensure alignment with project timelines and quality standards. 8. Document verification results, generate detailed reports, and present findings to stakeholders. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 3+ years of experience in SoC design verification within the VLSI domain. 3. Expertise in advanced verification methodologies, including UVM and SystemVerilog. 4. Strong understanding of SoC architectures, protocols, and interfaces (e.g., AXI, PCIe, USB, DDR). 5. Proficiency with simulation tools such as VCS, ModelSim, or Questa. 6. Experience with scripting languages (Python, Perl, TCL) for automation. 7. Familiarity with version control systems like Git. Excellent debugging and problem-solving skills, with a focus on delivering high-quality results. 8. Strong communication and collaboration skills to work effectively with cross-functional teams. Preferred Qualifications: 1. Experience with formal verification tools and techniques. 2. Familiarity with low-power verification strategies. Knowledge of hardware-software co-verification. 3. Exposure to machine learning or AI-based approaches in verification. Why Join Us? 1. Work on state-of-the-art SoC designs in a collaborative and innovative environment. 2. Opportunity to be part of a fast-growing company shaping the future of VLSI solutions. 3. Competitive compensation, professional growth opportunities, and a supportive work culture. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future !

Skills/Experience: Extensive experience in IP/SOC Verification. Must be proficient in System Verilog and UVM. Must have hands-on experience in the verification of the IP protocols such as PCIe/DDR/USB/Ethernet/CXL/HDMI/MIPI/DSI/CS/GLS/CPU Verification or any other high-speed protocols. Experience with scripting language (Python, Perl, TCL etc.) Experience in assembly language or C is a plus. Ability to create testbenches from scratch and own the complete verification including coverage of the subsystem/chip level. Strong debugging capabilities. Experience (years) : 3 - 12 Years Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

We make real what matters. This is your role. Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will get along with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We dont need superheroes, just super minds. You're an Electronics Engineer (B.Tech/ M.Tech) or related field from a reputed institute You've got phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well. You've sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. You are a great teammate, resilient and sincere, Enjoy learning new things and build knowledge base in new area.

Skills/Experience: Create emulation models from RTL / Netlist. Expertise in mapping designs to Zebu/Palladium/Haps emulation, improving model performance. Knowledge of the Palladium flow and experience in migrating design on Palladium. Good knowledge of runtime and debug skills. Identifying signals and taking wave dumps on palladium platforms and analyse the failures. Exposure to ARM/ARC cores and its architecture Exposure to AMBA bus architectures like AXI/AHB/APB Exposure to bug tracking tools like Jira and version control tools like Github, Bitbucket, GIT Exposure to Flash(NAND) and HDD(Hard disk) like storage technologies. Experience with Palladium like emulation platforms(Veloce or Zebu or Haps) Understanding of JTAG based debuggers Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Board Design. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: FPGA Design. Experience: 3-5 Years.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IJTAG. and MBIST/LBIST. Experience in Tessent based ATPG flow, GLS and Post-silicon-debug. Hands-on in Perl/Tcl/Python scripting. Excellent analytical, and problem-solving skills. Perform Core and SOC level ATPG to meet Automotive grade quality. Hierarchical ATPG retargeting and Pattern release for application on ATE. Perform SOC and Core level Timing/Non-timing GLS. Silicon bring-up, diagnosis and support for physical failure analysis. Enable Emulation of Gate level SCAN patterns. Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Lead the Architecture, Design and development of processor MMU (Memory management unit) for high- performance IBM Systems. - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the MMU feature enhancements. - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of experience in the memory management/ memory controller delivery leadership. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. Good understanding of industry trends & advances in - 8 to 15 years of relevant experience - At least 1 generation of experience in the memory management/ memory controller delivery leadership. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. Good understanding of industry trends & advances in architecting high bandwidth memory solutions.

End-to-end design and development of features for IBM high performance Mainframe and POWER processors and ASICs. Develop the feature, present the proposed architecture in the High level design discussions Estimate the overall effort to develop the feature Develop micro-architecture, Design RTL, Collaborate with the Verification, Physical design, FW teams to develop the feature Pre Silicon: Signoff the Design that meets all the functional, area and timing goals Post Silicon: Bringup and Validate the hardware functionality Required education Bachelor's Degree Required technical and professional expertise 1 to 3 years of professional experience Experience with HDLs- VHDL/ Verilog Understand and Design Power efficient logic. Drive design closure including test plan reviews and verification coverage Understand of logic synthesis, Physical Design concepts, Timing, and constraints Prior experience in and knowledge in one or more areas : I2C, I3C, SPI, AXI, AHB, APB, boot, security, debug and trace, OTP ROM, clocks and resets, silicon bringup

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Job Description We are looking for an experienced Design Verification Engineer to join our team and contribute to the verification of complex SoC/ASIC designs. The ideal candidate will have strong expertise in verification methodologies, testbench development, and debugging. Key Responsibilities: Develop and implement verification plans, environments, and testbenches using SystemVerilog/UVM. Write and execute test cases for functional, regression, and coverage-driven verification. Perform debugging and root cause analysis for design and verification issues. Collaborate with RTL design, architecture, and validation teams to ensure quality deliverables. Analyze functional coverage metrics and enhance test suites for improved quality. Work on assertion-based and formal verification techniques where applicable. Contribute to automation and scripting to streamline verification flows.

Education: Bachelors degree (BE/B.Tech)orMasters degree (ME/M.Tech) Roles & Responsibilities: Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team. Write and perform the test plan in close cooperation with the logical design team. Develop coverage models and verification environments using UVM-SystemVerilog C++. Write, maintain and publish the verification specification. Monitor, analyze and debug simulation errors. Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time. Produce a maintainable and reusable code across projects Required Skills and Experience Curious, demanding and rigorous. Mastering object oriented programming. Knowledge of UVM verification methodology (or equivalent) and SystemVerilog SystemC hardware verification languages Knowledge of Constraint-Random Coverage-Driven verification environments development in SystemVerilog C ++ (drivers monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp SVA) Knowledge of simulation tools and coverage database visualization tools Effective in problems solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints. Our Offering: Competitive salary package Leave Policies: 10 Days of Public Holiday (Includes 2 days optional) & 22 days of Earned Leave (EL) & 11 days for sick or caregiving leave. Benefit Plans (Insurance) Medical & Life & Accidental & EDLI

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: RTL coding.Experience: 3-5 Years.

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Mandatory Skills: ASIC Verification. Experience: 5-8 Years.

Design Verification: SV/UVM Test Bentch Developement Any Protocols: PCI Express or UCIe, CXL or NVM • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR or LPDDR or HBM) • 6+ years of hands-on DV experience in System Verilog/UVM. •Must be able to own and drive the verification of a block / subsystem or a SOC. •Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Physical Design: •In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. - Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Floor Planning/Innovus/Fusion Compiler Experience on programming in Tcl/Tk/Perl. Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. • Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. •Well versed with timing constraints, STA and timing closure. •Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. •Should have experience on programming in Tcl/Tk/Perl • Well versed with timing constraints, STA and timing closure. ASIC RTL Design: • 6+ years experience in RTL, Asic Coding, Design, IP Design, SOC Development, Lint, CDC • PCIe/DDR/Ethernet - Any One • I2C,UART/SPI - Any One • Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One • Scripting languages like Make flow, Perl ,shell, python - Any One DFT Engineer: Interface with ASIC design teams to ensure DFT design rules and coverages are met. Generate high-quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques. MBIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Work with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Analog Circuit Design Lead: 1. 6+ years of Experience in entire Analog IP development including circuit design, layout, AMS verification, and characterization. 2. Must have led the entire Analog IP development cycle and team. 3. Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc. 4. Analog/custom layout design in advanced CMOS process. 5. Ability to understand design constraints and implement high-quality layouts. 6. Conceptualize and implement chip-level mixed signal simulation environments (testbenches, run scripts, etc...). 7. Hands-on experience on lower FINFET technology nodes and design/PPA trade-offs.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: Semiconductor Integration. Experience: 3-5 Years.

As an ASIC Verification Lead at Eviden, a global leader in data-driven digital transformation, you will play a key role in integrating the ASIC functional verification team. The ASICs developed by Eviden include network controllers, routers, and cache coherence controllers for high-end and high-performance servers. Your expertise will be instrumental in utilizing Constraint-Random, Coverage Driven functional verification methodologies within the UVM verification framework to ensure thorough verification of complex ASIC designs. Your main responsibilities will include acquiring in-depth knowledge of ASIC architecture and microarchitecture by studying specifications and collaborating with architecture and logical design teams. You will actively participate in defining verification strategies and methodologies, developing simulation environments, and maintaining verification specifications. Collaborating closely with the logical design team, you will write and execute test plans, develop coverage models, and verification environments using UVM-SystemVerilog/C++. Furthermore, you will be responsible for monitoring, analyzing, and debugging simulation errors, as well as assessing simulation coverage results to enhance tests and meet coverage targets efficiently. Your role will also involve providing recommendations on tools and methodologies to enhance productivity, along with mentoring junior engineers to ensure maintainable and reusable code across projects. To excel in this role, you should have a proven track record of successful verification of complex SoCs or ASICs and a strong command of UVM or equivalent verification methodologies. Proficiency in developing Constraint-Random/Coverage-Driven verification environments in SystemVerilog/C++ is essential, along with expertise in simulation tools and coverage database visualization tools. Your ability to develop effective test plans, swiftly identify functional defects, and implement solutions under tight deadlines will be crucial. The ideal candidate will have a minimum of 7 years of experience and hold a Master's or Engineer's degree in Electronics and Communication Engineering. If you are passionate about driving innovation in ASIC verification and possess strong problem-solving skills, we invite you to join our dynamic team at Eviden and contribute to shaping the future of digital transformation. Let's grow together at Eviden.,

This role is for an ASIC Verification Engineer to join an IP or SoC verification team, with the ultimate goal of achieving first-pass silicon success. The ideal candidate will have solid experience in the verification of complex IPs or SoCs, and will be responsible for driving verification strategies, developing test environments, and ensuring design quality through rigorous analysis. Responsibilities Drive the overall verification strategy and write detailed Test Plans . Develop comprehensive Test Benches and Test cases . Analyze Code Coverage, Functional Coverage, and Assertions to ensure thorough verification. Utilize industry-standard tools, methodologies, and High-Level Verification Languages (HVLS). Skills Expertise in SoC Verification using C and SV/UVM or IP Verification using SV/UVM . Expertise in AMBA protocols like AXI/AHB/APB and experience working with ARM Processors . Expertise in Test Plan creation and verification technologies. Good knowledge of gate-level simulation and scripting languages like Perl and TCL . Excellent debugging and problem-solving skills . Experience in Low Power Verification is a plus. Verification experience in complex protocols like USB, PCIe, or DDR is highly desirable. Qualifications A B.Tech or M.Tech degree with solid experience in the verification of complex IPs or SoCs.

Job description ASIC Engineer, Architecture Responsibilities Work on advanced architecture, algorithms and models targeting Machine Learning solutions. Analyze and map data center workloads to ASIC architecture, as well as develop performance and functional models to validate the architecture. Implement and analyze algorithms and enhanced architecture for the data center Machine Learning accelerators. Implement various models needed for the validation of the accelerators. Create Machine Learning kernels to analyze the ASIC Architecture, and make the architecture optimal for ML workloads. Minimum Qualifications Currently has, or is in the process of obtaining, a Bachelors degree in Electrical Engineering, Computer Engineering or related field More than 2 years of industry experience and knowledge of Computer Architecture concepts such as processor architecture, memory systems and on-chip interconnection networks. Programming skills in C, C++ or related Object Oriented Programming Preferred Qualifications Master s or PhD degree in Electrical Engineering, Computer Engineering or related areas. Experience in modeling, and driving power and performance trade-offs in ASIC Architecture. Experience and knowledge in Machine Learning Silicon architectures.

Job description ASIC Engineer, Architecture Responsibilities Work on advanced architecture, algorithms and models targeting Machine Learning solutions. Analyze and map data center workloads to ASIC architecture, as well as develop performance and functional models to validate the architecture. Implement and analyze algorithms and enhanced architecture for the data center Machine Learning accelerators. Implement various models needed for the validation of the accelerators. Create Machine Learning kernels to analyze the ASIC Architecture, and make the architecture optimal for ML workloads. Minimum Qualifications Currently has, or is in the process of obtaining, a Bachelors degree in Electrical Engineering, Computer Engineering or related field More than 2 years of industry experience and knowledge of Computer Architecture concepts such as processor architecture, memory systems and on-chip interconnection networks. Programming skills in C, C++ or related Object Oriented Programming Preferred Qualifications Master s or PhD degree in Electrical Engineering, Computer Engineering or related areas. Experience in modeling, and driving power and performance trade-offs in ASIC Architecture. Experience and knowledge in Machine Learning Silicon architectures.