Senior Analog Layout Design Lead

Greetings from Eximietas Design! We are actively seeking Senior Analog Layout Design Engineers / Leads with 7-15 years of experience to join our expanding team in Bangalore, Hyderabad, and Visakhapatnam. The ideal candidate should have a strong background in lower FINFET technology nodes, particularly TSMC 5nm, to contribute to cutting-edge analog layout design. As a Senior Analog Layout Design Engineer / Lead, you will be responsible for optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance in layouts. You should have a solid understanding of how layout impacts circuit performance, such as speed and area, and the ability to implement high-quality layouts that meet tight design constraints. Key Skills & Requirements: - Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. - Solid understanding of how layout impacts circuit performance. - Ability to implement layouts meeting tight design constraints and delivering high quality. - Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. - Familiarity with scripting languages (PERL/SKILL) is a plus. - Strong communication skills and experience collaborating with cross-functional teams. If you find this opportunity intriguing or know someone who would be a good fit, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are excited to connect with talented engineers who are passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam Contact: +91 8088969910.,