Posted:1 month ago|
Platform:
Work from Office
Full Time
Role & responsibilities Job Title: RTL Design Engineer Experience: 5+ Years Job Description: We are hiring an experienced RTL Design Engineer to develop synthesizable Verilog/SystemVerilog code for complex SoCs. Candidate should be proficient in logic design, synthesis, and timing closure. Key Skills: RTL Design, Verilog, SystemVerilog, ASIC, SoC, Synthesis, Timing, STA, Lint, CDC
Qpeak Semiconductor
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