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Design Engineering Architech

Design Engineering Architech

Cadence

3 - 7 years

0 Lacs

noida uttar pradesh

Posted:1 week ago| Platform: Shine logo

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Skills Required

verilog systemverilog vhdl rtl dft post ist synthesis automation timing constraints lbist

Work Mode

On-site

Job Type

Full Time

Job Description

As a member of the Cadence team, you will have the opportunity to contribute to the world of technology by designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. Your responsibilities will include designing and implementing RTL for DFT IP, including POST and IST. You will play a key role in developing synthesis automation for DFT IP, which involves synthesis and timing constraints, RTL insertion, and verification. Additionally, you will be responsible for owning, maintaining, extending, and enhancing existing DFT IP such as LBIST. Join us in our mission to make a difference in the technology industry. Be a part of our team and help us tackle challenges that others cannot.,

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Design Engineering Architech