1277 System Verilog Jobs - Page 18

Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures Perform diagnostic and post-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree / Master's Degreein Electrical or Computer Engineering with 7+ years of ASIC design. Prior experience working with Verilog or System Verilog programming skills Experience with simulators/synthesis/static timing constraints and related tools (e.g., VCS, DC, PrimeTime) Experience with debugging and verification methodologies Preferred Qualifications: Understanding of Networking technologies and concepts Scripting experience (Python, Perl, TCL, shell programming) Experience with formal verification tools Experience with emulation

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 7+ years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Prior experience working with Gate level simulation, debugging with VCS and other simulators. Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Prior experience with Scripting skills: Tcl, Python/Perl. Preferred Qualifications: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Background in Test Static Timing Analysis Past experience with Post silicon validation using DFT patterns.

Project description This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. Responsibilities Drive the development of cutting-edge memory-related firmware projects, contributing to the creation of innovative solutions Collaborate with a highly regarded team to bring innovation to memory-related firmware, ensuring solutions are at the forefront of industry advancements Tackle complex challenges by employing strong problem-solving skills, enhancing firmware to meet evolving performance and reliability standards Skills Must have 5-12 years' experience. Strong with C language programming Working knowledge of git/gerrit Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Nice to have Understanding different vendor implementations and memory timing differences is a big plus

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Develop and optimize low-level operating system components, including drivers, kernel modules, and firmware. Perform pre-silicon debugging on FPGA, prototyping, and emulation platforms to validate design functionality. Lead post-silicon bring-up and validation activities on new silicon platforms. Work closely with hardware, architecture, and design teams to debug complex system issues across software and hardware boundaries. Develop test cases, debug tools, and automation for validation and verification purposes. Analyze and solve challenging issues involving hardware-software interactions. Document design, debug procedures, test plans, and results effectively. Skills Must have 5-15y exp Strong proficiency in C programming and data structures (Minimum skill rating8/10). Solid understanding of computer architecture and operating system fundamentals. Excellent problem-solving and debugging skills. Experience in pre-silicon environments (simulation, FPGA prototyping, emulation platforms). Experience with post-silicon validation and system bring-up. Familiarity with embedded systems, RTOS, and low-level software development. Ability to analyze hardware-software interaction issues. Nice to have Strong communication and collaboration skills.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Collaborate with design and verification teams to understand digital design specifications and ensure comprehensive verification coverage. Develop and execute verification plans for ASIC/FPGA designs using directed tests and/or SystemVerilog with UVM methodologies. Build and maintain testbenches, verification components, and assertion-based verification structures to validate complex digital designs. Perform simulation, debugging, and coverage analysis to ensure functional correctness and compliance with design requirements. Contribute to the automation of verification flows through scripting (Python, Perl, Bash) to improve productivity and consistency. Work in Unix/Linux environments for development, simulation, and regression testing activities. Document verification strategies, results, and maintain clear communication with cross-functional teams to support project milestones. Actively participate in code reviews and contribute to continuous improvement of verification methodologies and best practices. Skills Must have 1 position6+y, 1 position4+y Strong in digital design. Skills in ASIC / FPGA verification (directed test or System Verilog / UVM) A good knowledge of simulation flow Good basis in scripting Python, Perl, Bash.. Proficiency in Unix environment. Good communication skills Nice to have Bachelor's/Master's in ECE

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Develop System Verilog/UVM-based testbenches for block-level and system-level verification. Write and execute UVM test cases to verify functional correctness of RTL designs. Perform detailed functional coverage and code coverage analysis, and drive coverage closure. Debug simulation failures, root-cause issues, and work closely with design and verification teams for resolution. Collaborate with cross-functional teams to ensure successful verification closure within project timelines. * Develop and maintain scripts using Python or other scripting languages for automation, regression management, and data analysis (optional but preferred). Apply working knowledge of standard bus protocols such as AXI, APB, UART, and IJTAG for testbench development and debugging. Document verification plans, test specifications, test reports, and maintain traceability. Skills Must have 4-6y exp SV / UVM Test bench development and test cases coding Code and Functional coverage analysis and closure Work with team for verification closure Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage. Nice to have Experience with python or any other scripting language is a plus

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow’s idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your career meets tomorrow. Looking for Siemens EDA ambassadors Veloce Transactors (Accelerated Verification IPs) Veloce Transactor Group is part of Mentor Emulation Division R&D located in Noida. Group develops transactors (RTL based IPs/VIPs) for various protocol solutions in Networking, Display, Storage, Mobile, Automobile etc. At present Veloce Transactor Library supports more than 25 protocol solution and growing further. This is your Role Individual will be responsible for developing transactor (xVIP) solutions for CCIX or PCIe based interconnect technology. Primary responsibilities include understanding standard specifications, develop architecture and micro-arch for the design and writing a synthesized design using Verilog/System Verilog. Required Experience: We seek a graduate with at 1-5 years of relevant working experience with (BE/BTech/ME/MTech/MS) from a reputed engineering college. We value your experience on the protocol e.g. PCIe, USB, Ethernet, AMBA in Design or Verification. Good understanding of IP Verification Methodologies, Verification procedures and practices are plus! Experience in one or more verification techniques such as simulation, emulation, acceleration, formal, etc We value expertise in Verilog, SystemVerilog, and SystemC, as well as experience in developing RTL for FPGAs, ASICs, and IPs, as this will greatly contribute to the quality of our products. We expect candidates to be able to build verification test plans and environments, develop test cases, utilize VIPs, and efficiently debug defects identified during verification processes. We consider exposure to object-oriented programming languages like C++ an advantage, and experience in scripting languages such as Perl will also be valuable in automating tasks and improving efficiency. You need to engage with customers for Deployment and R&D assistance. We've got quite to offer, how about you We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, colour, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. At Siemens, we are always challenging ourselves to build a better future. We have some of the most inquisitive minds working across the world, re-imagining the future and doing extraordinary things. #LI-EDA

Looking for Siemens EDA ambassadorsLead Software Engineer for Product Validation and Customer support for PowerPro We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and betterJoin us – whichever path you take, we’re looking forward to seeing your point of view! As an integral part of the Siemens EDA team, you will contribute to Siemens EDA by growing efficiency and customer satisfaction Siemens EDA’s Power platform. This is an ambitious position that will assist in growing Siemens's EDA business in India. About the group: We are in DDCP (Digital Design Creation Platform group) which include top industry tools like Tessent, PowerPro, Catapult, Aprisa. We are part of DPRS (Devops, Product, Release & Support group) inside DDCP which works on cutting edge tools like PowerPro. Our team is responsible for Product Validation, Customer Support & Release work for PowerPro tool. PowerPro is the commercially available RTL sequential power optimization and power analysis tool. We are a team driven with lots of energy, synergy and passion. Job Responsibilities: Work as an integral part of Product Validation and Customer Support team to validate and educate feature of PowerPro. Being the internal end-user of the tool, validate all features and report issues. Development of test plan and writing test cases. Take measures to improve quality of Product and test environment. Support and debug customer test design methodologies using our products. Participate in architecture reviews and involve in defining features prototyping. Get along with field teams to understand customer design flows requirements and propose measures to optimize and improve flow results. Analyse customer reported bugs and plug gaps in testing, incorporate newer designs/flows. Use technical expertise to respond to customer inquiries, demonstrate products. Provide field application support to customer. Role may involve interaction with customers on critical issues to narrow down the problem. Lead 1-2 junior folks or Intern. guide them and help them in day-to-day activities. Technical Skills (Must have): B.Tech (EE/ECE) or M.Tech (VLSI/Microelectronics) with working experience of 5+ Years. Good knowledge of ASIC design flows, Verification, Digital Logic, Synthesis, HDL Languages Verilog/VHDL/SV. Good understanding of low-power SOC design principles. Experience with class of products like simulation, synthesis, Place & Route, etc. Excellent problem-solving and debugging capability. Technical Skills (Good to have): Low Power concepts, RTL/Gate Simulation and Emulation, SPEF, Different tech nodes. Knowledge of one of the scripting languages like Perl, Tcl. Python will be a plus. Worked on designs to apply power solutions, UPF etc. Different Tool knowledge like Power Artist, Joules, Prime Power/PTPX, Questa, VCLP, DC etc. Worked in EDA CAD team for RTL Soft Skills: Excellent verbal and written communication skills. Self-starter, motivated and strong teammate. Team Contributor, Quick learner. Hard working, sincere and committed to work. Team leader We’ve got quite a lot to offer. How about you A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Transform the everyday Accelerate transformation #li-eda #li- Hybrid

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Mandatory Skills: VLSI Physical Verification. Experience: 5-8 Years.

Job description Design Verification Engineer (4 to 15 Years) SoC/IP Verification Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune] Experience: 4 to 15 Years Openings: 4 Positions Preferred - Immediate to 45 Days (Notice Period) ACL Digital is hiring experienced Design Verification Engineers to work on leading-edge processor-based SoCs and IPs. Strong understanding of design verification methodologies (UVM, SV, etc.) Experience with industry-standard protocols (AXI, DDR, PCIe, etc.) Familiarity with ASIC and SoC design flows. Proficiency in scripting languages (Python, Perl) Experience with simulation tools and debuggers. Strong problem-solving and analytical skills Communication and collaboration skills to work effectively with cross-functional teams Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: AMBA, AXI, PCIE, USB, MIPI

Develop Detailed Documentation for Verification Strategy and Test Plan for IP, Subsystem and SoC. Directed and Random Verification at IP, Subsystem and SoC Level for complex ARM / RISC-V processor based MCU, MPU products, Mixed Signal SoCs, Processors, Memory Subsystems, Connectivity Platforms, Analog, Security Acceleration, General Peripherals. Perform Functional and Code Coverage Analysis. Experience and Skills Required 5 to 15 years of experience in IP SoC Verification. Expertise in Verilog, System Verilog, UVM, Constrained Random Verification, Formal Verification, Mixed Signal Verification, Post-Layout Gate Level Simulations, Code Coverage and Functional Coverage analysis. Development of Verification IP and Testbenches. Experience with AMS simulations desired. Must have strong debug and analytical capabilities, root cause analysis. In-depth understanding of SoC Design Flow, RTL Implementation, Analog Circuit models. Soft Skills Strong analytical, problem-solving, and hands-on skills. Self-driven and thrives when facing open-ended tasks. Start-up mentality: fast-paced, flexible and team-oriented. Good written and verbal communication skills with great documentation skills. Flexibility to work with varied schedules and tolerance for ambiguity.

Front End Integration of Digital, Analog IPs and Subsystems to build complete SoC Netlist. IOMUX and Padring generation and integration. Design of SoC Specific Logic IPs. Perform quality checks like Lint and CDC at SoC level. Implement all feedback from Verification and Physical Design teams for all changes required. Develop SoC level Testbench for RTL and Postlayout Simulations. Collaborate with ATE and Test teams and deliver test patterns for Probe and Package level testing. Support Verification and Post-Silicon Debugging of issues. Experience and Skills Required 10-15 Years Experience in front end integration for complex SoCs. Strong scripting skills. Hands on experience in RTL coding, Lint, CDC. Experience in developing IOMUX and Padring. Expertise in developing testbench for SoC to support directed and random verification. Experienced with working with ATE teams for delivery of test patterns. Soft Skills Strong analytical, problem-solving, and hands-on skills. Self-driven and thrives when facing open-ended tasks. Start-up mentality: fast-paced, flexible and team-oriented. Good written and verbal communication skills with great documentation skills. Flexibility to work with varied schedules and tolerance for ambiguity.

Define SoC Function, Performance requirements. Define SoC Connectivity, Interconnectivity, Memory Map, Interrupt Map, Pin Muxing, Power Management, SoC Clock Distribution, SoC Debug. Define Data Flow and Use Cases. Maintain SoC Die Size and Power Estimates and ensure competitive PPA. Close collaboration with SoC Design and Verification Teams. Experience and Skills Required 10 to 15 years of experience in SoC / IP Design, IP Architecture SoC Architecture. Experience with ARM Microcontrollers, Memory and Interconnect technologies. Hands-on experience with defining Clocking Strategy, Power Management and Low Power strategies. Must be familiar with various Connectivity standards, SoC Security. Hands on experience with IP Design / Micro Architecture required. Experience with Signal Processing IP is preferred. Good Understanding of SoC Front End and Back End Design Flow, SoC Verification and Validation flows. Must have deep understanding Software requirements - Secure Boot, RTOS, Device Drivers. Soft Skills Strong analytical, problem-solving, and hands-on skills. Self-driven and thrives when facing open-ended tasks. Start-up mentality: fast-paced, flexible and team-oriented. Good written and verbal communication skills with great documentation skills. Flexibility to work with varied schedules and tolerance for ambiguity.

Development of Specifications, Micro Architecture, RTL Development for Digital IPs. Setup and use standard EDA tools for Verification, Lint CDC, Synthesis, Power Analysis tools for Verification and Ensuring PPA for IP developed. Conduct Reviews for Documentation, RTL and Verification Tests. Experience and Skills Required 5 to 15 years of experience in SoC/IP Design. Expertise in Writing Detailed IP Specifications, Micro Architecture, IP design, Subsystem and SoC level integration. Expertise on RTL Development. Follow Coding Standards, expertise on Lint, CDC tools, verification and debugging of test cases, code and functional coverage analysis. In-depth knowledge of Clocking Methodology, Low Power Implementation. Hands on experience on writing constraints and exceptions, performing Synthesis, Timing Analysis and Design for Test Implementation. Experience of power partitioning and usage of CPF/UPF. Exposure to IP Design for ARM Microcontrollers based SoCs. Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB). Knowledge of one or more of the interface protocols, PCIe, DDR, Ethernet, I2C, UART, SPI. Experience in Matlab Simulations and Implementing Signal Processing IPs like Digital Filters, Math Functions or FFT engines. Experience in developing Security IPs for various Encryption standards. Experience in implementing On-chip Memory and Flash controllers. Soft Skills Strong analytical, problem-solving, and hands-on skills. Self-driven and thrives when facing open-ended tasks. Start-up mentality: fast-paced, flexible and team-oriented. Good written and verbal communication skills with great documentation skills. Flexibility to work with varied schedules and tolerance for ambiguity.

Design Verification Engineer - Specialised in Protocol like; PCIe/Ethernet/DDR/LPDDR/HBM Location: Noida, UP / Bangalore, India Experience: 3-10 Years Job Description: Experience in interconnect protocol PCIe/ Ethernet. Experience in Memory protocol DDR/LPDDR/HBM; HBM is preferred. AXI/ACE/CHI understanding, [AXI is must] Understanding of DMA usage. Strong in SV/UVM. Experience in the usage of standard VIP in TBs (preferably Synopsys) AI/ML network understanding (good to have). Additional knowledge of perl/tcl scripting will be an advantage. Must Bachelors Degree in Electrical, Electronics or Computer Engineering

About Marvell . Your Team, Your Impact For Central Engineering BU What You Can Expect Essential Responsibilities (not limited to): Responsible for understanding the logic, develop hitlist, verification environment, testcases etc. , required for verifying the logic, individually Implement verification methodologies for testbench development Develop scripts required for running simulations and regressions and debug fails Document the verification plan and verification documentation Plan functional coverage/code coverage, analyze and improve coverage Review and update verification environment and testcases Report, track and close logic issues Work and communicate effectively with global team Work with designers and FW engineers to enable better verification What Were Looking For Essential qualifications: Must have good digital logic understanding and fundamentals of digital design. Candidate must have excellent skills in digital logic verification and hardware description language (VHDL or Verilog), Strong knowledge in object oriented programming using languages such as System Verilog Must have hands on experience in hardware verification methodologies such as UVM or OVM, Must be familiar with verification test planning and coverage driven verification closure, Verification strategies for directed and randomised testing and assertions Must have good experience in using simulation tools and proficiency in simulation debug techniques. Strong knowledge / experience in building the verification environment from specification and should have spec to hardware bring-up experience. Must have hands on knowledge on test-bench development and automation, bug tracking, and regression mechanisms Should be able to act as the team lead to determine methods and procedures on new assignments and coordinate activities of other team members to ensure successful project completion. Preferred skills: Experience in High Speed SerDes, clock data recovery based PHYs, Asynchronous clock domain crossing verification. IP architecture and verification knowledge Experience in scripting languages such as Perl Gatelevel simulation and AMS simulation knowledge Experience with Linux operating system Experience with industry simulation tools Good communication skills and quick learning ability. Knowledge of standard configuration management system like CVS or SVN Hands on scripting knowledge Education: Bachelor s degree in Electronics Engineering or related fields and 7-8 years of related professional experience. Master s degree in VLSI Design with 5 -7 years of experience. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

Must Have: SV/UVM Test Bentch Development Any Protocols: (PCI Express or UCIe, CXL or NVM • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR or LPDDR or HBM) • 8+ years of hands-on DV experience in System Verilog/UVM. •Must be able to own and drive the verification of a block / subsystem or a SOC. •Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. •Must have extensive experience in verification of one or more of the following: •PCI Express or UCIe, CXL or NVM • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR or LPDDR or HBM • ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages • Power Aware Simulations using UPF

Job Title: Senior / Lead Design Verification Engineer Experience: 6 10 years Location: Siruseri, Chennai (Work from Office only) Industry: Semiconductor / VLSI Employment Type: Full-time / Permanent Key Responsibilities: Perform functional verification at block and chip level for complex ASIC/SoC designs. Build UVM-based testbenches from scratch for new IPs or subsystems. Develop and execute detailed verification test plans based on design specifications. Write directed and constrained-random test cases; debug simulation failures. Perform coverage analysis (functional and code) and drive closure. Work with RAL (Register Abstraction Layer) to verify register-level functionality. Develop and validate assertions (SVA) for protocol and functional correctness. Collaborate closely with RTL, DFT, and GLS teams to ensure alignment across design phases. Participate in multiple tapeouts, ensuring verification quality and delivery. Required Skills: • Strong hands-on experience with SystemVerilog and UVM methodology. • Solid knowledge of SoC/ASIC architecture and verification lifecycle. • Hands-on experience in writing testbenches, stimulus, checkers, monitors, and scoreboards . • Strong debugging skills using simulation tools like VCS, Questa. • Experience with functional and code coverage. • Familiarity with Register Abstraction Layer (RAL) modeling and verification. • Excellent analytical and problem-solving skills. • Strong communication and teamwork abilities. Interested candidates kindly forward your resume to swetha.s@thompsonshr.com

Develop verification testbench components for chip/module level using System Verilog, C/C++. Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment. Define and execute detailed verification plan from spec working with architects, designers, system engineers. Write tests, Debug tests, automate regression scripts and regression environment. Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout. Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required. Excellent debugging skills in both SW and ASIC hardware. Must be good in building verification environments preferably using Verilog, System Verilog, UVM, C/C++/PLI etc. Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus. Experience with simulators like ncVerilog (Incisive), VCS, Eldo and debug tools like Verdi/Debussy. Good understanding of latest formal verification techniques, assertions, properties is a plus. Understanding or prior experience with Industry standard protocols like USB/SPI/SATA/Ethernet/DisplayPort/SRIO/DDR/PCIE/DDR4/LPDDR4/DFI etc is a definite plus. Understanding or Prior Experience in ARM/Tensillica Processor platforms is a definite plus. Good written and oral communication skills. Ability to clearly document plans.

PMTS - GFX Verification Technical Lead Role: We are currently seeking a highly skilled Principal Member of technical staff (PMTS) Verification engineer for GFX top level end-to-end verification. Responsibilities: In this role, he/she would be the technical lead responsible for driving content, quality and debug throughput of top-level debugs coming from simulation, emulation, and post-silicon debugs. Working with architects and design leads and driving quality test plans Developing verification infrastructure and needed improvements Developing content strategy for quality. Driving DV closure to meet schedule with quality Working with each domain (sub-system) lead and guide them to get better quality and debug throughput. Helping management with risk assessment on features, quality, and schedules Working with sub-system DV leads to identify potential areas of formal verification Requirements: BS +14 years or MS +12 years work experience preferred. Should have end to end GFX/Compute verification experience and system knowledge. Experience with advanced verification methodologies and languages like UVM, system Verilog. Familiarity with all Design areas and tools and confirmed understanding of design/technology interactions Good understanding of memory hierarchy, caches, address translations schemes. Good understanding of general dram technologies and address translation schemes Familiarity with GFX pipeline and GPU design is plus Familiarity with Computer organization/architecture. Strong analytical/problem solving skills and pronounced attention to details. Formal property-based verification knowledge is an added plus. Must be a self-starter, and able to independently drive tasks to completion. Good teamwork and communications skills are required Academic credentials: B.E/B.Tech or M.E/M.Tech degree in ECE / Electrical Engineering / Computer Engineering #LI-NS1

Required Qualifications System Verilog, UVM, C Scripting languages (Python, Tcl, Perl) Understanding of bus protocols (AXI, AHB, APB, etc.) Proven written and verbal technical communication skills Ability to collaborate in a team environment Excellent analytical and problem-solving skills. Experience 8- 10 years Preferred Qualifications From-scratch development of IP or SoC testbenches Familiarity with RISC-V architecture, Functional Safety Standards (ISO 26262) Background with power-ware (UPF) and gate-level simulations (GLS) Ownership of complete verification cycle (verification planning -> coverage closure) in a project Use of formal verification, particularly connectivity, to confirm SoC connectivity requirements Knowledge of UVM Register Abstraction Layer (RAL) and integration of 3rd party VIPs

Job Title Required Qualifications System Verilog, UVM, C Scripting languages (Python, Tcl, Perl) Understanding of bus protocols (AXI, AHB, APB, etc.) Proven written and verbal technical communication skills Ability to collaborate in a team environment Excellent analytical and problem-solving skills. Preferred Qualifications From-scratch development of IP or SoC testbenches Familiarity with RISC-V architecture, Functional Safety Standards (ISO 26262) Background with power-ware (UPF) and gate-level simulations (GLS) Ownership of complete verification cycle (verification planning -> coverage closure) in a project Use of formal verification, particularly connectivity, to confirm SoC connectivity requirements Knowledge of UVM Register Abstraction Layer (RAL) and integration of 3rd party VIPs Experience 4-5 years

Tasks: Verificationof SoCs, automotive ASICs, subsystems, IPs. Application of Metric-driven Verification (MDV) and/or Formal Verification methodologies Developing and tracking of Verification plans Develop verification environments from scratch Create VIP Integration of VIP ( Verification-IP ) Measure and analyze regression results Continuous improvement of verification methods/tools/flows/processes together with EDA partners Requirement: 5 to 10 years of Experience in Digital RTL verification using System Verilog and UVM. Sound knowledge of constrained random verification, UVM/OVM Sound knowledge in System Verilog. Experience of developing functional coverage code, coverage analysis. Experience of developing verification environments from scratch is desirable. Good hands on experience with cadence/Synopsys/Mentor tools. Exposure to configuration management, bug tracking tool etc. Knowledge of scripting language, Perl TCL etc. Good experience with AMBA protocols Working knowledgeon ARM processor-based subsystem/SoC verification Formal verification experience is a desirable but not must. Must have been a part of one or more ASIC/SoC tape outs. Knowledge of VHDL/VERILOG. SPECMAN knowledge is a desirable but not must.

Role & responsibilities: Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT tools Extensive experience in Back-end design Experience on Mentor Graphics EDA flow is an added advantage Responsible for development and support of Projects. Responsible for Debugging the source codes in Verilog, SV, and UVM. Responsible for Training Delivery and Support Preferred candidate profile Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design 3 to 8 years industry/teaching experience Good communication & presentation skill

{"company":" About Eridu AI Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is looking to hire highly motivated and talented professionals for its RD center in Bengaluru to join our world-class team. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI s solution and value proposition have been widely validated with several hyperscalers. The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World s leading micro-LED display company and developer of the first augmented reality contact lens) . Visit our website to learn more about our impressive list of investors, advisors and leadership team. ","role":" Position Overview We are seeking an RTL Packet Processing Engineer to help define and implement our industry-leading Networking IC. If youre a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. Responsibilities Packet Processing Design: Design and architect solutions for high-speed networking device, focusing on latency optimization, and quality of service (QoS) support. Prior experience with CAMs, and routing tables. Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Conduct thorough testing and validation to ensure functionality and reliability. Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics. Protocol Support: Provide support for various networking protocols and standards related to input and output queues, including Ethernet. Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, working closely with cross-functional teams, including hardware engineers, firmware developers, and system architects. Qualifications ME/BE with a minimum of 8-15 years of experience. Working knowledge of system Verilog, and Verilog is Mandatory . Prior experience with ownership of memory subsystems. Proven expertise in designing and optimizing packet pipelining and QoS mechanisms, for high-speed networking devices. Solid understanding of ASIC design methodologies, including simulation, and verification tools (e.g. Synopsys, Cadence). Experience with Ethernet/PCIe networking protocols. Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues. Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.