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1.0 - 2.0 years

3 - 4 Lacs

Chennai

Work from Office

Job title: FPGA Design Engineer (Telecom/Aerospace) Organization Name: NEC Corporation of India Ltd. Reporting Relationship: Reporting to Project Manager Location: Chennai/Hybrid Experience 1 -2 years Job Summary: We looking for an experienced and highly talented FPGA design engineer with strong telecom and Aerospace expertise at NEC Mobile Network Excellence Center (NMEC), Chennai Scope of work Implementing FPGA code on the target hardware & testing with other system components and software RTL Design, Implementation, Testing, Integration and delivery of FPGA based hardware systems for Telecom and Aerospace Applications Involve in R&D activities demonstrating Proof of Concept in various technologies for aerospace related design techniques. Qualifications BE/B.Tech/M.E/M.Tech or its Equivalent Experience 1 -2 years Domain Expertise Proficient in FPGA design flows using Xilinx tools, including compilation, simulation, synthesis, debugging, performance optimization, and implementation of advanced features. Strong knowledge of hardware description languages such as Verilog, VHDL, and System Verilog. Skilled in developing verification environments using self-checking testbenches, Bus Functional Models (BFMs), checkers/monitors, and scoreboards in VHDL/Verilog. Familiarity with designing common control interfaces such as AMBA AXI, UART, SPI, I C, DDR, Ethernet, and USB. Hands-on experience with hardware measurement and debugging tools including oscilloscopes, signal analyzers, and JTAG emulators. Good to Have Experience integrating Soft IP or Hard IP like GTX/GTH transceivers, MAC, DMA controller, PCIe Gen3, CPRI, JESD, or FFT IP cores Proficiency in scripting languages for automation, including Perl, TCL, or Python. Exposure to standard FPGA hardware bring-up procedures and testing methodologies. Experience in linting, static timing analysis, equivalence checking, and clock domain crossing (CDC) verification.

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8.0 - 13.0 years

25 - 50 Lacs

Bengaluru

Work from Office

Roles and Responsibility Senior CPU System Verification Engineer Role Overview: Focused on validating CPU subsystems at SoC level, including coherency, interconnect protocols, and system-level features. Key Responsibilities: Architect and lead UVM-based SoC verification environments Define SoC-level verification plans and coverage strategies Drive verification of memory subsystems, MMU, and coherency protocols Debug and resolve critical functional issues and performance bottlenecks Mentor junior engineers and review test/coverage implementation Required Skills: 8+ years of experience in system-level verification Strong knowledge of SystemVerilog, UVM, and SVA Deep understanding of interconnect protocols (AXI, CHI, ACE) Proven ability to debug simulation failures and track coverage metrics Experience with regression infrastructure, scripting, and waveform tools

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6.0 - 8.0 years

7 - 13 Lacs

Mysuru, Bengaluru

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Job Description: We are looking for experienced DV Lead Engineers with a strong background in SystemVerilog, UVM, and protocol-based SoC/IP verification . The ideal candidate will have excellent debugging and leadership skills, with hands-on experience in building testbenches and leading verification teams. Key Responsibilities: Build comprehensive test plans , test cases , and functional coverage from specification documents Architect and develop UVM-based testbenches and verification environments Work with high-speed protocols such as AXI, AHB, APB, PCIe Hands-on debugging and simulation using Synopsys and Cadence tools Mentor junior team members, collaborate cross-functionally, and lead project execution Good to Have: Scripting and automation (Perl/Python/TCL) Experience with UPF simulations , GLS , and Formal Verification Exposure to SoC-level verification Strong communication and leadership abilities

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4.0 - 7.0 years

9 - 21 Lacs

Bengaluru

Work from Office

Strong in digital design. Skills in ASIC/FPGA verification(directed test or SV/UVM) A good knowledge of simulation flow. Good scripting knowledge Perl/python Apply &Share your Resume to mansoor@hisoltech.com

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7.0 - 10.0 years

17 - 32 Lacs

Bengaluru

Work from Office

Lead the verification planning and execution for complex SoC designs. Define and implement testbenches using SystemVerilog/UVM methodologies. Work closely with architecture, design, and firmware teams to understand the design and develop test strategies. Drive block-level and full-chip verification , including IP integration . Perform coverage analysis , debug , and triage failures . Develop and maintain automation scripts to improve verification workflows. Mentor and guide junior verification engineers and drive best practices across the team. Ensure delivery on schedule with high quality and coverage metrics.

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6.0 - 10.0 years

0 Lacs

vijayawada, andhra pradesh

On-site

You are invited to join Coventine Digital Private Limited as a Senior/Lead Design Verification Engineer based in Siruseri, Chennai. In this role, you will have the opportunity to work closely with a top-tier client and play a pivotal role in developing next-gen chip-level verification environments utilizing System Verilog and UVM methodologies. This is a full-time position that requires you to work from the office. As a Senior/Lead Design Verification Engineer, you will be responsible for functional verification at both block and chip levels for complex designs. Your tasks will include developing verification test plans based on detailed design specifications, constructing UVM-based simulation environments using System Verilog, analyzing coverage to ensure completeness, implementing assertion-based verification for functional robustness, validating register-level behaviors with RAL, collaborating across functions to synchronize design and verification milestones, and creating testbenches for simulation and performance efficiency. The ideal candidate for this role should have a minimum of 6 to 10 years of experience in design verification. You should be well-versed in System Verilog, UVM, and ASIC verification methodologies. If you are passionate about making a significant impact in chip-level verification and are ready to contribute to cutting-edge projects, we encourage you to apply for this position by sending your resume to Venkatesh@coventine.com or by contacting us directly. Join our team at Coventine Digital Private Limited and be part of a dynamic environment where your skills and expertise in design verification will be valued and recognized. Take the next step in your career and explore the exciting opportunities that await you in the field of chip design and verification. #Hiring #DesignVerification #SystemVerilog #UVM #ChipDesign #ASICVerification #VerificationEngineer #ChennaiJobs #HardwareDesign #CareerGrowth #Recruitment,

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5.0 - 9.0 years

0 Lacs

noida, uttar pradesh

On-site

Qualcomm India Private Limited is a leading technology innovator that is dedicated to pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Hardware Engineer at Qualcomm, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. This includes a wide range of tasks such as bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To qualify for this role, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field. In this position, you will have the opportunity to closely interact with the product definition and architecture team, develop implementation strategies to meet quality and performance goals for the Sub-system, and define various aspects of block-level design. Your responsibilities will also include leading a team of engineers on RTL coding for Sub-system/SOC integration, function/performance simulation debug, driving Lint/CDC/FV/UPF checks to ensure design quality, and developing Assertions as part of white-box testing-coverage. You will work with stakeholders to discuss collateral quality, identify solutions/workarounds, and deliver key design collaterals like timing constraints and UPF. Desired skills for this role include a good understanding of low power microarchitecture techniques and AI/ML systems, thorough knowledge of Computer system architecture, experience in high-performance design techniques, and trade-offs in Computer microarchitecture. You should also be knowledgeable in NoC Design principles, define Performance and Bus transactions based on use cases, work with Power and Synthesis teams, have expertise in Verilog/System Verilog, and experience with simulators and waveform debugging tools. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require an accommodation during the application/hiring process, please contact disability-accommodations@qualcomm.com or Qualcomm's toll-free number. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those concerning the protection of confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities directly with Qualcomm. Staffing and recruiting agencies are not authorized to use this site. Unsolicited resumes or applications from agencies will not be accepted. For further information about this role, please contact Qualcomm Careers directly.,

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8.0 - 15.0 years

0 Lacs

karnataka

On-site

Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is looking to hire highly motivated and talented professionals for its R&D center in Bengaluru to join our world-class team. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today's AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software, and systems to deliver solutions that improve AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI's solution and value proposition have been widely validated with several hyperscalers. The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems. We are seeking an RTL Packet Processing Engineer to help define and implement our industry-leading Networking IC. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. Responsibilities include Packet Processing Design, Implementation and Testing, Performance Optimization, Protocol Support, and Troubleshooting and Debugging. The ideal candidate should have ME/BE with a minimum of 8-15 years of experience, working knowledge of system Verilog and Verilog, proven expertise in designing and optimizing packet pipelining and QoS mechanisms for high-speed networking devices, solid understanding of ASIC design methodologies, experience with Ethernet/PCIe networking protocols, strong analytical and problem-solving abilities, as well as excellent verbal and written communication skills. At Eridu AI, you'll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.,

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0.0 - 1.0 years

10 - 15 Lacs

Hyderabad

Work from Office

Digital Electronics Testing Internship Hyderabad, Telangana, India Interns/Temp Intern Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our internship programs offer real-world projects, hands-on experience, and opportunities to collaborate with passionate teams globally. Explore your interests, share your ideas, and bring them to life while shaping your career path within our inclusive culture that fosters innovation and collaboration. Engineer your future with us!. Play Video Job Description Category Interns/Temp Hire Type Intern Job ID 7073 Remote Eligible No Date Posted 13/07/2025 We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world. Internship Experience: At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide and having fun in the process! Youll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today! Mission Statement: Our mission is to fuel today s innovations and spark tomorrow s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive both at work and beyond. What You ll Be Doing: Writing constrained-random System Verilog test benches using UVM/VMM. Examining functional, assertions and code coverage. Debugging RTL and gate-level simulations failures. Testing products and flows to ensure quality and reliability. Verifying fixed issues to confirm effective resolution. Collaborating with the engineering team to identify and address technical challenges. Documenting test cases, procedures, and results for transparency and learning. Providing feedback for continuous tool and process improvements Participating in team discussions to brainstorm solutions and share innovative ideas. What You ll Need: Currently pursuing / recent graduate of B-Tech or M-Tech in Electronic Engineering, Computer Science, or a related field (penultimate or final year is preferred). Strong analytical and problem-solving skills. Basic knowledge of digital electronics concepts. Excellent communication skills. Meticulous attention to detail. Ability to work collaboratively in a team environment. Proactive attitude and eagerness to learn. Key Program Facts: Program Length: 12 months Location: Hyderabad, India Working Model: On-site Type of Internship: Industrial Placement Full-Time/Part-Time: Full-time Start Date: July/August2025 Equal Opportunity Statement: Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Get an idea of what your daily routine around the office can be like Explore Hyderabad View Map Hiring Journey at Synopsys Apply As an applicant your resume, skills, and experience are being reviewed for consideration. Phone Screen Once your resume has been selected a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. Interview You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via Zoom. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

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4.0 - 7.0 years

5 - 9 Lacs

Bengaluru

Work from Office

Since June 2021, frog is part of Capgemini Invent . frog partners with customer-centric enterprises to drive sustainable growth, by building and orchestrating experiences at scale, while harnessing the power of data and technology. Were inventing the future of customer experiences by delivering market-defining business models, products, services, brand engagements and communications. Joining frog means youll be joining the pond, a global network of studios, each with a thriving in-person and vibrant virtual culture. frogs are curious, collaborative, and courageous, united by our passion for improving the human experience across our areas of expertise, while each bringing our unique and diverse skills and experiences to the table. We draw on our global reach and local knowledge to solve complex problems and create innovative, sustainable solutions that touch hearts and move markets. frogs prize humour, positivity, and community just as highly as performance and outcomes. Our culture is open, flexible, inclusive, and engaging. Working at frog means being empowered to meet the moment, and Make Your Mark on every project, in your studio, your community and the world at large. Equal Opportunities at frog Frog and Capgemini Invent are Equal Opportunity Employers encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status, or any other characteristic protected by law.

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5.0 - 10.0 years

3 - 7 Lacs

Bengaluru

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Job Title:DEVOPS- AWS Glue, KMS, ALB , ECS and Terraform/TerragruntExperience5-10YearsLocation:Bangalore : DEVOPS, AWS, Glue, KMS, ALB , ECS, Terraform, Terragrunt

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5.0 - 9.0 years

10 - 20 Lacs

Bengaluru

Work from Office

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com Position Name DV Engineer -GLS Position type: Permanent Total Exp: 5-7 years Notice Period: Immediate to 15days Work Location: Bangalore KEY RESPONSIBILITIES: "Key Responsibilities: Develop and implement scalable UVM-based verification environments Lead and execute GLS (Gate-Level Simulation)timing-aware and glitch-sensitive validation is a core part of this role Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure Analyze waveforms, root-cause issues, and contribute to debugging complex logic Requirements Required Skills: Solid hands-on experience with SystemVerilog and UVM methodologies Strong understanding and application of GLS (Gate-Level Simulation) techniques Experience with CDC verification and asynchronous domain handling Familiarity with tools such as VCS, Questa, Incisive Scripting knowledge (Python, Perl, or Shell) is a plus" AMD (Dont Share AMD Profiles) Preferred candidate profile

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8.0 - 15.0 years

0 Lacs

karnataka

On-site

As a RTL Packet Processing Engineer at Eridu AI India Private Limited, a subsidiary of Eridu Corporation based in Saratoga, California, USA, you will play a crucial role in defining and implementing industry-leading Networking IC. Your primary responsibility will be to design and architect solutions for high-speed networking devices with a focus on latency optimization, quality of service (QoS) support, CAMs, and routing tables. By implementing designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks, and conducting thorough testing and validation, you will contribute to the development of cutting-edge Networking devices. Your role will involve analyzing and optimizing pipelining architectures to enhance performance metrics, providing support for various networking protocols and standards related to input and output queues, including Ethernet, and troubleshooting and resolving complex issues related to packet queuing. Collaboration with cross-functional teams, including hardware engineers, firmware developers, and system architects, will be essential to investigate and address networking challenges effectively. To qualify for this position, you should hold a ME/BE degree with a minimum of 8-15 years of experience, possess working knowledge of system Verilog and Verilog, and demonstrate prior experience with ownership of memory subsystems. Your expertise in designing and optimizing packet pipelining and QoS mechanisms, familiarity with ASIC design methodologies, simulation, and verification tools, and experience with Ethernet/PCIe networking protocols will be crucial. Strong analytical and problem-solving abilities, attention to detail in troubleshooting and debugging, and effective communication skills will enable you to collaborate efficiently in a team environment and present technical information to diverse audiences. Joining Eridu AI will offer you the opportunity to contribute to the future of AI infrastructure, working alongside a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for this role will be determined based on your skills, experience, qualifications, work location, market trends, and compensation of employees in comparable roles.,

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5.0 - 9.0 years

0 Lacs

noida, uttar pradesh

On-site

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. To qualify for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field. In this position, you will closely interact with the product definition and architecture team, develop implementation strategies to meet quality goals, define block-level design aspects, lead a team of engineers on RTL coding, drive design quality checks, and work towards delivering key design collaterals. Desired Skillset for this role includes a good understanding of low power microarchitecture techniques, AI/ML systems, computer system architecture, high-performance design techniques, NoC Design principles, Verilog/System Verilog, SOC DFT, and logic design principles. You will also work with stakeholders to discuss collateral quality, identify solutions, and collaborate with Power and Synthesis teams on use cases. Qualcomm is an equal opportunity employer committed to providing an accessible process for individuals with disabilities. If you require accommodation during the application/hiring process, you may contact Qualcomm. It is expected that employees abide by all applicable policies and procedures, including security and confidentiality requirements. Staffing and Recruiting Agencies are advised that Qualcomm's Careers Site is for individuals seeking a job at Qualcomm, and unsolicited submissions will not be considered. For more information about this role, please contact Qualcomm Careers.,

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6.0 - 10.0 years

0 Lacs

vijayawada, andhra pradesh

On-site

You are invited to join Coventine Digital Private Limited as a Senior/Lead Design Verification Engineer in Siruseri, Chennai! In this role, you will have the opportunity to work directly with a prominent client, contributing to the development of next-generation chip-level verification environments utilizing System Verilog and UVM methodologies. As a Senior/Lead Design Verification Engineer, you will be responsible for functional verification at both block and chip levels for complex designs. You will play a crucial role in developing verification test plans based on detailed design specifications and constructing UVM-based simulation environments using System Verilog. Additionally, you will conduct coverage analysis to ensure the validation's completeness, implement assertion-based verification to guarantee functional robustness, and collaborate across teams to align design and verification milestones. Your tasks will also involve working with RAL to validate register-level behaviors, creating testbenches for simulation, and optimizing performance efficiency. If you have 6 to 10 years of relevant experience and are eager to make a significant impact in chip-level verification, we encourage you to apply for this permanent position. This is a Work from Office opportunity located in Siruseri, Chennai. Immediate joiners are preferred. Don't miss this chance to be part of a dynamic team and contribute to cutting-edge chip design projects. Send your resume to Venkatesh@coventine.com or contact us directly to explore this exciting career opportunity. Join us in shaping the future of hardware design and advancing your career in the field of design verification. #Hiring #DesignVerification #SystemVerilog #UVM #ChipDesign #ASICVerification #VerificationEngineer #ChennaiJobs #HardwareDesign #CareerGrowth #Recruitment,

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5.0 - 15.0 years

0 Lacs

noida, uttar pradesh

On-site

We are seeking experienced Senior/Lead ASIC Verification Engineers to join our Noida-VIP team. With 5 to 15 years of experience in Verification, particularly using industry-standard protocols and methodologies, this role offers a challenging opportunity for individuals well-versed in System Verilog, Verilog, and Object-Oriented Programming. As a successful candidate, you will have demonstrated your ability to lead the development of reusable Verification environments on at least 2 projects using VMM, OVM, or UVM methodologies. Your expertise should extend to protocols such as UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory. Your responsibilities will include contributing to the development of the VIP, reviewing and signing off on VIP development and updates, and collaborating with Architects and methodology experts to address issues and drive architectural and methodological perspectives. If you are a proactive and reliable professional with a passion for Verification, we invite you to share your updated CV with us at taufiq@synopsys.com. Feel free to refer anyone who may be interested in this exciting opportunity as well. At Synopsys, we value Inclusion and Diversity, considering all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability. Join us in shaping the future of technology.,

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5.0 - 9.0 years

0 Lacs

pune, maharashtra

On-site

As a SoC RTL Design Engineer at Lattice Semiconductor, you will join the HW design team focused on IP design and full chip integration. This exciting position offers the opportunity to be part of a dynamic team where you can contribute, learn, innovate, and grow. Located in Pune, India, this full-time role will concentrate on RTL design, full chip integration, and projects within similar time zones, providing ample opportunities to work on cutting-edge technologies. Your responsibilities will include working on RTL design with best-in-class coding styles, algorithms, and utilizing Verilog and System Verilog. You will also be involved in SoC integration and quality checks such as lint, CDC, RDC, SDC, etc. Collaborating closely with the architect and micro-architect team, you will define design specifications and work towards accelerating design time and improving quality through logic design of key blocks and full chips. To be successful in this role, you should have a BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science, or equivalent, along with at least 5 years of experience in driving logic design across various silicon projects. Expertise in SoC integration, defining micro-architecture, and experience with 3rd party IP selection is required. Additionally, familiarity with FPGA designs, ARM processor, AXI, AMBA bus, ENET, PCIE, safety and security protocols, and debug architecture will be advantageous. You should be an independent worker and leader with strong problem-solving abilities, capable of working with multiple groups across different sites and time zones. Occasional travel may be required as part of the role. Lattice Semiconductor values its employees and offers a comprehensive compensation and benefits program to attract, retain, and reward top talent in the industry. Lattice Semiconductor is a service-driven developer of innovative low-cost, low-power programmable design solutions with a global workforce that is dedicated to customer success and driven to achieve excellence. If you are passionate about working in a fast-paced, results-oriented environment and believe you can thrive in a demanding yet collegial atmosphere, Lattice Semiconductor may be the perfect fit for you. Feel the energy at Lattice Semiconductor.,

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5.0 - 10.0 years

30 - 45 Lacs

Bengaluru

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5+y in processor verification Proficiency in UVM SystemVerilog for developing verification environments,testbenches Validate ARM M-series,RISC-V processor designs C programming for processor-level test EDA for simulation,debugging,coverage analysis

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2.0 - 5.0 years

6 - 10 Lacs

India, Bengaluru

Work from Office

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. This role is based in Bengaluru. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come We make real what matters! This is your role Deploy Siemens EDA ProFPGA prototyping software and hardware solutions at customers and guide the customers to successful design bring-up Work closely with R&D to solve problems, review product specs, and find good general solutions that improve the overall product Train AE’s and customers on the solutionWin pre-sales engagements in cooperation with the technical sales teams Successfully deploy our solutions at early customer sites. This means educating the customer on best practices and tool requirements. It also means working with R&D to make the tool improvements necessary for the customer’s success. Ensure existing customers maximize the value they receive from the solution by developing and enhancing methodology that exploits the solution’s capabilities Ensure customers are kept up-to-date with the latest enhancements Provide customer requirements to R&D and marketing Work with QA and Docs to help them create tests and documentation that will improve our solutions Create examples and tutorials that are shipped with our products. Develop and/or refine methodology employed in creating and using prototypes and maximizing the value of our prototyping solution We don’t need superheroes, just super minds! A good understanding of FPGA based hardware prototyping platforms Working knowledge of multi FPGA prototyping flows(Synthesis, partitioning, PnR, runtime and debug) Practical insights into the application and usage of FPGA prototyping systems Knowledge of design mapping, testbench mapping and transactor development Expertise of hardware/software debug solutions related to FPGA prototyping Knowledge of test bench acceleration, ICE and co-model solutions Highly proficient in HDLs (Verilog/SV) for RTL design and HVLs (SV/UVM) for verification Solid background in Functional Verification, RTL synthesis and PnR flows Conversant with SoC design and architecture concepts Good communication and inter-personal skills. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Siemens Software. Where today meets tomorrow #LI-EDA #LI-Hybrid

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3.0 - 7.0 years

9 - 13 Lacs

Noida, India

Work from Office

Looking for Siemens EDA ambassadors Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the Increasingly complex world of chip, board, and system design. Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based onImplementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join the team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation! We make real what matters. This is your role. Questa verification IP’s help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will work well with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We don’t need superheroes, just super minds. We are seeking Electronics Engineers (B.Tech/M.Tech) or professionals from related fields, graduated from reputed institutes, who possess strong expertise in verification engineering and bring 3-7 years of hands-on experience to the table. You've sound knowledge of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. We are phenomenal teammates, resilient and sincere, with a passion for learning new things and building our knowledge base in new areas! A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare. Transform the everyday! #LI-EDA #LI-Hybrid #DVT

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2.0 - 6.0 years

10 - 14 Lacs

Noida, India

Work from Office

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! Key Responsibilities In this role, you will Design and developAI-powered agentsusingLLMs, LangChain , vector databases, andretrieval-augmented generation (RAG). Build intelligent systems thatunderstand natural language queriesandautomate complex workflows. Integrate and experiment withML pipelines,data-driven decision-making, andreinforcement learningfor adaptive systems. Prototype and productize tools that leverage code understanding,profiling, anddata analysis. Collaborate closely with AI researchers, UX designers, and backend teams to translate ideas into working products and robust features. Work onprompt engineering,few-shot learning, andtool use orchestration What We’re Looking For Must-Have Hands-on experience withAI/ML frameworks(e.g., PyTorch , TensorFlow, Scikit-learn). Strong working knowledge ofLangChain ,RAG pipelines, andvector stores. Strong understanding and experience in application ofDeep Learningmodels likeANNsandtransformers. Experience in developingAI agents or copilotsthat interface with tools or external APIs. Proficiency inPython; familiarity with software design patterns and clean code. Practical experience indata preprocessing,feature engineering, andmodel evaluation. Familiarity withLLMs(OpenAI, LLaMA , Claude, etc.) andprompt engineeringbest practices. Ability toidentify AI use-cases, conceptualize solutions, and drive from prototype to production. Strong proficiency in programming languages like C/C++ and Python, along with strong foundations in algorithms and data structures. Good to Have Background or interest inDigital Design,SystemVerilog , orEDA tools(can be learned on the job). Basic knowledge ofcompilers,parallelism, orprofilingtools is a bonus. Why Join Us Work oncutting-edge AI R&D projectswith real product impact! Be part of astartup-like team within a global tech company. Opportunity to lead innovation, publish internally, and drive industry-first solutions. Competitive compensation, flexibility, and a collaborative culture. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color , national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #DVT

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10.0 - 15.0 years

4 - 8 Lacs

Bengaluru

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As a Linux Development Engineer, you will be responsible for bringup of IBM Power Hardware. You will apply your deep expertise in Hardware bring-up process, PCIe, Root Complex during your journey at the Linux Technology Center. You will also interact with opensource communities to upstream your work as well as work in close collaboration with hardware teams. This includes Bringup of new versions of Power Hardware on Simulators/QEMU, Hardware Configurations bring-up, PCIe/PHB Bring-up, Inband communication with BMC, System dump management, JTAG debugging, XIVE interrupt controllers and OpenCAPI/CXL. Required education Bachelor's Degree Required technical and professional expertise 10 to 15 years of experience in working on projects related to Hardware Bring-up Root Complex, Protocol training, Link Equalization, PCI/PCIe driver, PCI enumeration, XIVE, QEMU, PLDM, IOMMU Strong programming skills in C. Strong Operating systems skills Deep expertise in hardware bring-up / debugging. Deep expertise in computer systems architecture.

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2.0 - 7.0 years

6 - 10 Lacs

Bengaluru

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As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Required technical and professional expertise -2+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

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5.0 - 10.0 years

25 - 40 Lacs

Chennai, Bengaluru, Delhi / NCR

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Design Verification Engineer (5-7 years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Design Verification Engineer (7-10 years’ experience) Company: HCL Tech Job Summary: We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 7-10 years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement

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8.0 - 13.0 years

20 - 35 Lacs

Hyderabad

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Our Team: Semtech Corporation is a leading supplier of analog and mixed-signal semiconductors for high-end consumer, enterprise computing, communications, and industrial equipment. As our future market opportunities have increased in recent years, we have continued to invest in disruptive analog platforms and have created innovative new solutions for a wide range of leading-edge products. The Wireless analog/digital and LoRa System teams located in our Neuchtel and Grenoble offices have unique expertise in system level solutions for Low Power Wireless Area Network (LPWAN) products. These teams are the worlds leaders for long range, low power, battery powered, wireless communication. The Semtech expertise cover a unique field from the antenna, analog & digital IC design, low power system, protocol, and cloud-based solutions. You will be part on the journey of the new LoRa and LoRaWAN System architecture. Job Summary: We are seeking an experienced and dynamic SoC Verification Manager to lead our verification team. The successful candidate will manage a team of up to 5 verification engineers, overseeing the verification of RTL designs to ensure the highest quality and performance of our wireless SoCs. This role involves team technical leadership, project management, and hands-on verification tasks. Responsibilities: Lead and manage a team of verification engineers, providing guidance, mentorship, and performance feedback.(20%) Ensure the definition and implementation of test and verification plans.(20%) Collaborate with design, architecture, and other cross-functional teams to ensure alignment on project goals and requirements.(10%) Monitor and analyse coverage reports to ensure thorough verification.(10%) Identify and resolve verification issues and bugs, ensuring timely project delivery.(10%) Continuously improve verification processes, methodologies, and tools.(10%) Manage project schedules, resources, and deliverables to meet deadlines.(10%)Lorawa Oversee the writing and debugging of SystemVerilog assertion.(10%) Minimum Qualifications: 8+ years of relevant experience in SOC verification. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in RTL design verification and team management. Proficiency in System Verilog and assertion-based verification. Strong understanding of test and verification plan definition and implementation. Experience with coverage-driven verification and coverage report generation. Familiarity with industry-standard verification tools (e.g., VCS, QuestaSim). Experience with SoC designverification. Knowledge of HVL methodology (UVM/OVM) with the most recent experience in UVM. Experience with formal verification. Experience taping out large SoC systems with embedded processor cores. Hands-on verification experience of Bus Fabric, NOC, AMBA-AHB/AXI based bus architecture in a UVM environment. Knowledge of Low Power Verification. Excellent problem-solving skills and attention to detail. Desired Qualifications Experience in wireless SoC design and verification. Knowledge of scripting languages (e.g., TCL, Python, Perl) for automation. Familiarity with version control systems (e.g., Git).

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