RTL Design Engineer

Proxelera

2 - 3 years

4 - 5 Lacs

bengaluru

Posted:20 hours ago| Platform:

Apply

Skills Required

soc simulation digital design vhdl rtl design design compiler axi modelsim asic synthesis rtl coding ahb system verilog architecture rtl compiler synthesis sta design concepts cdc c ip rtl uvm verilog cadence asic design lint fpga design synopsys

Work Mode

Work from Office

Job Type

Full Time

Job Description

Proficiency in RTL designs using Verilog/SystemVerilog/VHDL based on specifications.
Solid understanding of digital design concepts, including pipelining, clock domain crossing (CDC), and reset strategies.
Experience with industry-standard tools for synthesis, linting, and STA (e.g., Synopsys Design Compiler, Mentor Questa, or Cadence Genus).
Collaborate with system architects to understand requirements and translate them into micro-architectures.
Perform design optimization for performance, power, and area (PPA).
Work with verification teams to define test plans and debug issues in simulations and emulation environments.
Address synthesis, timing, and functional issues through RTL modifications.
Create and maintain design specifications, architecture diagrams, and documentation for IP or SoC blocks.
Provide support for integration and bring-up activities.

More Jobs at Proxelera

Business Development Manager

Bengaluru

8.0 - 13.0 yrs

INR 0 - 0 Lacs

DV Engineer (PCIE)

Bengaluru

5.0 - 10.0 yrs

INR 0 - 0 Lacs

DV MBIST Verification Engineer

Hyderabad

4.0 - 9.0 yrs

INR 0 - 1 Lacs

DFT MBIST Engineer

Hyderabad

3.0 - 5.0 yrs

INR 0 - 0 Lacs

Design and Verification Engineer

Hyderabad

5.0 - 10.0 yrs

INR 10 - 20 Lacs

Mock Interview

Practice Video Interview with JobPe AI

Start Job-Specific Interview

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.