100 Design Compiler Jobs

Role: RTL Lead Experience: 8-12 years Location: HYD & BNG JD: General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required E...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. To...

Position: Physical Design Engineer Experience: 4+ yrs Location: Bangalore, Hyderabad Notice Period: Preferably 0 to 45 days Summary: Strong expertise in Physical Design and RTL-to-GDSII implementation flow, including synthesis, floor planning, place-and-route, timing closure, and sign-off. Proven ability to close full-chip and block-level designs from RTL to GDSII, addressing timing, noise, power, IR drop, physical verification, and equivalence checks. Hands-on experience with advanced technology nodes (7nm, 5nm, and below), managing challenges related to performance, power, and area (PPA). Proficient in Synopsys and Cadence tool suites, including Fusion Compiler, ICC2, Design Compiler, Prim...

General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ...

We are seeking multiple experienced Semiconductor Design and Verification Engineer with expertise across multiple domains in the semiconductor lifecycle from Physical Design (PNR) and Test Engineering (DFT) to Digital Verification (DV). The ideal candidate will have a proven track record of working on complex SoC designs, including ARM subsystems, PCIe interfaces, MBIST, Scan Insertion, and ATPG. The role offers a unique opportunity to contribute across the full chip design and verification process, with leadership responsibilities for teams of engineers. Key Responsibilities Physical Design (PNR): Handle full-chip Place and Route (PNR), including timing convergence, congestion analysis, Clo...

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on exp...

The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow's future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. What You'll Do End-to-End ASIC Implementation Lead...

General Summary: Responsibilities will include To be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 12+ years of work experience in ASIC IP cores design Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and ...

Please find JD for required job profile. Bachelors or Masters Degree with a strong VLSI Background Minimum 4 years of experience in Synthesis . Worked on 7nm/5nm/Future sub-micron Technologies. Hands on experience in Physical Synthesis with Multi corner & Multi-mode, Low Power, Performance and Area Goal using Fusion Compiler or Genus . Hands on experience in Logic equivalence check and low power check debugging and clean up using Conformal LEC or Formality. Familiar with pre-STA timing analysis using Primetime or Tempus. Familiar with low power check using Conformal Low Power or VCLP tool. Experience in verifying constraints quality and completeness. Understanding of UPF & Low power concepts...

General Summary: Responsibilities will include To be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 4-8 years of work experience in ASIC IP cores design Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and ...

General Summary: Responsibilities will include To be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 8 to 10 years of work experience in ASIC IP cores design Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture ...

Proficiency in RTL designs using Verilog/SystemVerilog/VHDL based on specifications. Solid understanding of digital design concepts, including pipelining, clock domain crossing (CDC), and reset strategies. Experience with industry-standard tools for synthesis, linting, and STA (e.g., Synopsys Design Compiler, Mentor Questa, or Cadence Genus). Collaborate with system architects to understand requirements and translate them into micro-architectures. Perform design optimization for performance, power, and area (PPA). Work with verification teams to define test plans and debug issues in simulations and emulation environments. Address synthesis, timing, and functional issues through RTL modificat...

Your role and responsibilities Design and implement synthesis flows using Synopsys Design Compiler. Collaborate with cross-functional teams to align methodology with design requirements. Drive innovation in SoC design methodologies, tools, and flows. Provide technical leadership and support to resolve RTL, DFT, and synthesis-related issues. Interface with EDA vendors to evaluate and integrate new tool features. Ensure methodology scalability and robustness across multiple projects. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Bachelors or Masters degree in Computer Science, Electronics Engineering, or VLSI Design. 5"“8...

You will be responsible for the following tasks: - Experience in Logic design, micro-architecture, and RTL coding is a must - Hands-on experience with SoC design and integration for SoCs - Proficiency in Verilog/System-Verilog - Knowledge of AMBA protocols such as AXI, AHB, APB, SoC clocking/reset/debug architecture, and peripherals like USB, PCIE, and SDCC - Understanding of Memory controller designs and microprocessors is an added advantage - Hands-on experience in constraint development and timing closure - Collaborate closely with the SoC verification and validation teams for pre/post Silicon debug - Hands-on experience in Low power SoC design - Experience in Synthesis and understanding ...

Responsibilities: * Perform timing analysis using Primetime, Design Compiler & Genus. * Collaborate with design team on ASIC synthesis and timing closure. * Implement innovative techniques for improved performance. Health insurance Provident fund Food allowance

Requirement Details: Role: Synthesis Engineer Experience: 4+ years Location: Bangalore (Preferred) Skill Set: Hands-on experience in logic synthesis using Design Compiler Strong understanding of timing , low-power requirements , and constraints validation

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Front End Synthesis and Implementation Engineer - Job Description Front End Synthesis and Implementation Engineer Join the India team of a cutting-edge, well-funded storage startup in Silicon Valley as the Front End Engineer responsible for implementing complex SoCs using ARM architecture. As a Front End Engineer, you will work on SoC RTL and its implementation and quality checks such as synthesis, lint, CDC, and other aspects of the SoC implementation process. You will be involved in checks and flow management for both high-performance, multi-million gate complex IPs and SoCs. You will also be responsible for Power, Performance, and Area (PPA) analysis and optimization, as well as ensuring ...

General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ...

Job Details: Job Description: As an IP Structural/Physical Design Engineer, you will be working alongside Elite IP and SoC design teams to deliver next-generation Xeon products and related IPs for Server markets. We are looking for candidates with experience as physical design engineers as part of the Structural Design Expert Team in the IP organization. You will be fluent in all aspects of IP physical design flow from high-level block design to synthesis, place and route and timing and power convergence to build a design database that is ready for manufacturing. Your responsibilities will include all aspects of RTL2GDSII physical design flow convergence including but not be limited to: Over...

General Summary: Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primet...

General Summary: Responsibilities will include To be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 12+ years of work experience in ASIC IP cores design Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and ...

As an ASIC/SoC Design Engineer at Qualcomm India Private Limited, you will be responsible for Logic design, micro-architecture, RTL coding, and integration for complex SoCs. Your expertise in Verilog/System-Verilog and knowledge of AMBA protocols such as AXI, AHB, and APB will be crucial. You will collaborate with verification and validation teams, work on low power SoC design, multi-clock designs, and asynchronous interfaces. Your experience with tools like Lint, CDC, Design compiler, and Primetime will be essential for successful ASIC development. Additionally, your understanding of constraint development, timing closure, and synthesis concepts will be beneficial. **Key Responsibilities:**...

As a Senior SoC Design Engineer at Qualcomm India Private Limited, you will be utilizing your 10-16 years of experience in SoC design. Your responsibilities will include working with AMBA protocols such as AXI, AHB, and APB, understanding SoC clocking/reset/debug architecture, and dealing with peripherals like USB, PCIE, and SDCC. It is crucial to have expertise in memory controller designs, microprocessors, constraint development, and timing closure. Collaboration with SoC verification and validation teams for pre/post Silicon debug will be an integral part of your role. Additionally, hands-on experience in Low power SoC design, Multi Clock designs, Asynchronous interface, and proficiency i...

As an experienced Logic Design Engineer at Qualcomm India Private Limited, your role will involve the following key responsibilities: - Hands-on experience in Logic design, micro-architecture, and RTL coding, with a strong emphasis on SoC design and integration for complex SoCs. - Proficiency in Verilog and System-Verilog, along with a solid understanding of AMBA protocols like AXI, AHB, and APB, as well as SoC clocking, reset, debug architecture, and peripherals such as USB, PCIE, and SDCC. - Knowledge of Memory controller designs, microprocessors, and experience in constraint development and timing closure. - Collaboration with the SoC verification and validation teams for pre/post Silicon...