Lead Design Verification Engineer

Job Area:
Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Position: Lead DV Engineer
Location: Noida
Experience: 5-8 years

The role generally entails :

Understand IP specs and able to extract TB components and Testplan documents Monitors, scoreboards, sequencers, and sequences, that utilize scripts, System Verilog, UVM, UVM_REG, and methodologies to increase the rate with which bugs are found and resolve Demonstrated technical expertise in functional verification of complex designs including test planning, test bench development, stimulus generation, checking, and functional coverage Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, must be willing to dig into fail and understand what is happening Ensure timely Functional and Code coverage closure

Following skillset is required

• Strong hands-on experience withUVMandSystemVerilog
• Deep understanding ofAMBA protocols(AXI, ACE, AHB)
• Proficiency inPythonorPerlscripting
• Exposure toHW Resiliency algorithms,Coherent Protocols(ACE, CHI)