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CAPRUS IT PRIVATE LIMITED
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ASIC/RTL Design Engineer - SoC

ASIC/RTL Design Engineer - SoC

CAPRUS IT PRIVATE LIMITED

5 - 9 years

0 Lacs

hyderabad telangana

Posted:2 weeks ago| Platform: Shine logo

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Skills Required

logic design rtl coding soc design integration verilog systemverilog lint cdc synthesis formal verification axi ahb apb pcie ethernet usb ddr scripting automation multi clock designs asynchronous interface asic development eco fixes amba protocols soc clocking reset architecture verification cycle functional coverage matrix comprehensive test plan regression management dut integration verification ip development system buses system verilog assertions release process simulations regressions

Work Mode

On-site

Job Type

Full Time

Job Description

As an experienced professional in Logic design and RTL coding, you will be required to have hands-on experience in SoC design and integration for complex SoCs. Your expertise in Verilog/System-Verilog and Multi Clock designs, including Asynchronous interface, will be crucial for this role. Additionally, your familiarity with tools in ASIC development such as Lint and CDC will be essential. Your responsibilities will include understanding standards/specifications, developing architecture, documenting implementation level details, and working on every aspect of the verification cycle. You will be responsible for compliance with the latest methodologies, developing Verification IPs, defining Functional Coverage matrix, and creating a Comprehensive Test plan. Regression management, functional coverage closure, DUT integration, and verification for IP delivery sign-off will also be part of your role. Leading a small team and possessing strong verification concepts are key aspects of this position. Your skills should encompass a strong knowledge of Verilog, SystemVerilog, and UVM, along with experience in UVM-based Verification IP development. Hands-on experience with AMBA AXI/AHB/APB System buses and PCIe/Eth/USB/DDR etc. is required. Proficiency in System Verilog Assertions, scripting for automation, release processes, simulations, and regressions is also expected. Desired skills and experience include being a DV Engineer, Design Verification, or Verification Engineer. Excellent oral and written communication skills, creativity, curiosity, motivation to learn, and good collaboration skills are essential for success in this role. Please note that the company is described as proactive, creative, curious, and motivated to learn and contribute with good collaboration skills.,

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ASIC/RTL Design Engineer - SoC