153 Logic Design Jobs

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Lead the Architecture, Design and development of processor MMU (Memory management unit) for high- performance IBM Systems. - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the MMU feature enhancements. - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of experience in the memory management/ memory controller delivery leadership. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. Good understanding of industry trends & advances in - 8 to 15 years of relevant experience - At least 1 generation of experience in the memory management/ memory controller delivery leadership. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. Good understanding of industry trends & advances in architecting high bandwidth memory solutions.

End-to-end design and development of features for IBM high performance Mainframe and POWER processors and ASICs. Develop the feature, present the proposed architecture in the High level design discussions Estimate the overall effort to develop the feature Develop micro-architecture, Design RTL, Collaborate with the Verification, Physical design, FW teams to develop the feature Pre Silicon: Signoff the Design that meets all the functional, area and timing goals Post Silicon: Bringup and Validate the hardware functionality Required education Bachelor's Degree Required technical and professional expertise 1 to 3 years of professional experience Experience with HDLs- VHDL/ Verilog Understand and Design Power efficient logic. Drive design closure including test plan reviews and verification coverage Understand of logic synthesis, Physical Design concepts, Timing, and constraints Prior experience in and knowledge in one or more areas : I2C, I3C, SPI, AXI, AHB, APB, boot, security, debug and trace, OTP ROM, clocks and resets, silicon bringup

The people are the culture. We encourage a culture of passion for technology solutions that impact businesses. We also make sure that our people pursue their individual passions. Working with us means you get an in-depth understanding of a range of industries and emerging technologies that help us build solutions that are futuristic and impactful. More importantly, the experience of being at MarvyLogic may help you evolve as a person toward enjoying a more fulfilling life. Minimum BE/BS degree in Electrical/Electronics/Computer science required. At least 5-10 years of logic design and RTL coding experience with sound knowledge on verification and implementation concepts. Experience in physical layer ASIC architecture, micro-architecture development, design and debug. Ability to code readable, maintainable, verifiable and synthesizable logic in Verilog and/or SystemVerilog. Experience with lint, synthesis, CDC, STA, formality, ECO process, tool flows, and scripting. Knowledge in one or more of the following areas, a definite plus: Ethernet (layer 2/3/4 protocols, GMII/XGMII, integration of PHY layer), DSP fundamentals/Filter/FFT design/Datapath design/Error Control Coding, Computer architecture/Processor fundamentals. Preferred Qualifications: Strong knowledge of ASIC design methodologies and flows. Ability to proactively take on responsibilities and competent to work in a start-up environment. Worked with product development companies and having seen at least a couple of tape-outs. Experience with silicon bring-up in the lab and debugging is a definite plus. Experience with FPGA realizations of higher complexity designs. Ability to work with teams spread across geography with excellent communication skills. Responsibilities: Develop key blocks of logic in a next-generation physical layer/mixed signal SOCs. Perform hardware feasibility analysis and come up with a micro-architecture specification helping it map to a high performance, implementable design. Work with verification, DFT, synthesis, circuits, backend implementation teams to realize quality implementation.,

You will play a crucial role in developing Interface and Analog IPs for internal ASIC or external customers. This will involve hands-on experience with Hard Analog or PHY blocks on circuit design using the latest finfet nodes like 16nm and 7nm. Your responsibilities will include driving processes to establish a solid IP Development methodology for successful outcomes with customers. Additionally, you should be able to provide support for multiple customers and IP Deliveries, possessing strong knowledge in all aspects of IP integration such as logic design and verification, physical design, packaging, test, and characterization. To excel in this role, you should have a minimum of 6 years of experience in IP Design and delivery of complex analog, mixed signal IPs or PHYs. Previous exposure to DDR, HBM, and SerDes is highly preferred. A Masters Degree or equivalent in Electronics and Computer Engineering is the minimum educational qualification required, with a preference for a PhD. Expertise in the complete ASIC and IP development life cycle is essential, along with a desire for hands-on engineering experience throughout the ASIC/IP development flow. Excellent verbal and written communication skills are crucial, including the ability to engage effectively with customers and vendors. As part of our commitment to employee well-being and satisfaction, we offer a comprehensive benefits package that includes competitive compensation, Restricted Stock Units (RSUs), opportunities for advanced education from Premium Institutes and eLearning content providers, medical insurance, wellness benefits, educational assistance, advance loan assistance, and office lunch & snacks facility. At Alphawave Semi, we prioritize Diversity & Inclusivity. We are an equal opportunity employer and encourage applications from all qualified individuals, including visible minorities, Indigenous People, and persons with disabilities. If you require accommodation as a qualified job applicant, we will work with you to provide reasonable accommodations tailored to your specific needs. If your application is selected to proceed in our hiring process, you will have the opportunity to request accommodations.,

You will be responsible for Logic design, micro-architecture, and RTL coding, with hands-on experience in SoC design and integration for complex SoCs. It is essential to have expertise in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, as well as SoC clocking, reset, debug architecture, and peripherals such as USB, PCIE, and SDCC. Understanding Memory controller designs and microprocessors will be advantageous. Collaborating closely with SoC verification and validation teams for pre/post Silicon debug is a key aspect of this role. Your role will require hands-on experience in Low power SoC design, Multi Clock designs, and Asynchronous interfaces. Proficiency in using ASIC development tools such as Lint, CDC, Design compiler, and Primetime is necessary. An understanding of constraint development and timing closure will be a plus. Experience in Synthesis and knowledge of timing concepts will also be beneficial. Additionally, experience in creating padring and collaborating with the chip-level floorplan team is desirable. You must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 6 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 5+ years of relevant experience or a PhD with 4+ years of relevant experience will also be considered. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. Reasonable accommodations will be provided upon request to support individuals with disabilities in the hiring process. The company expects all employees to adhere to relevant policies and procedures, including security protocols and confidentiality requirements. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies. Staffing and recruiting agencies, as well as individuals being represented by an agency, are not authorized to submit profiles, applications, or resumes through the Qualcomm Careers Site. For more information about this role, please reach out to Qualcomm Careers.,

About QpiAI: QpiAI is at the forefront of discovering optimal AI and Quantum systems across various industries including Life sciences, Healthcare, Transportation, Finance, Industrial, and Space technologies. Specializing in building full stack Enterprise Quantum Computers, the Quantum hardware team at QpiAI is dedicated to the design and characterization of Quantum Processor, Cryogenic Quantum Control Circuits, RF Control Hardware, and QpiAI ASGP. We are looking for a talented Hardware Design Engineer to join our innovative team. Together, we aim to develop cutting-edge custom hardware for Quantum computers that have the potential to revolutionize various sectors. If you are a self-driven individual with a solid grasp of building complex SOC and IPs, possess a deep understanding of client requirements, and are familiar with different development cycles, then this opportunity is tailored for you. Responsibilities: - Engage in micro-architecture development and document specifications. - Implement designs in RTL and collaborate with the verification team to ensure functionality. - Utilize logic design expertise to optimize performance and power objectives. - Produce a synthesis/timing clean design while cooperating with the physical design team for a routable and physically implementable design. Requirements: - Bachelor's degree in electrical engineering or computer engineering. - 3+ years of experience in chip design development for complex designs. - Proficiency in logic design, Verilog, and/or System-Verilog, with a strong understanding of physical design and VLSI. - Excellent interpersonal skills and a team player mindset. - Familiarity with design reuse, including RTL, constraints, and waiver. - Experience in handling timing constraints and exceptions. - Ability to conduct standard quality checks such as LINT and CDC. Join us at QpiAI and be part of a dynamic team driving advancements in Quantum computing hardware to shape the future of technology across multiple industries.,

Qualcomm India Private Limited is seeking a candidate with a minimum of 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FV. The ideal candidate should have experience in Logic design/micro-architecture/RTL coding, along with hands-on experience in designing and integrating complex multi clock domain blocks. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, clocking/reset/debug architecture are necessary. Experience in Multi Clock designs and Asynchronous interface is a must, as well as familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime. Collaboration with Design verification and validation teams for pre/post Silicon debug is expected, and hands-on experience in Low power design is preferable. Additionally, experience in Synthesis and understanding of timing concepts for ASIC is essential. The minimum qualifications for this position include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in the relevant fields with 2+ years of experience or a PhD with 1+ year of experience would also be considered. Qualcomm is an equal opportunity employer committed to providing accessibility to individuals with disabilities throughout the application/hiring process. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. Employees are expected to adhere to all applicable policies and procedures, including security and confidentiality requirements. Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use the site or submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not bear responsibility for any fees related to such submissions. For more information about this role, please contact Qualcomm Careers.,

As a CPU Performance Management FW Developer at Qualcomm India Private Limited, you will be part of the Engineering Group focusing on Hardware Engineering. Your role involves collaborating with a team to enable power management solutions for Qualcomm's custom CPUs. You will work internally to define standard-driven solutions, implement embedded firmware, and manage the performance of the CPU subsystem. Additionally, you will play a key role in characterizing and tuning this solution for all Qualcomm SoCs utilizing custom CPUs. In this position, you will work closely with hardware power management and firmware development teams. You will have the opportunity to engage with third parties for platform enablement and provide input to SoC and platform architects for future designs. Responsibilities include driving firmware design, implementation, and verification in pre-silicon and post-silicon environments. You will assist in defining CPU performance management solutions for future Qualcomm CPUs, collaborate with open-source communities, and contribute to support for processor architectures, device drivers, and firmware features. Furthermore, you will help identify skill requirements, participate in hiring engineers, and collaborate with other teams on platform bring-up, debug, diags, and firmware lifecycle. To qualify for this role, you should have a Bachelor's degree in Electrical, Computer Engineering, or Computer Science with at least 5 years of experience in embedded firmware development. Proficiency in writing and debugging C and assembly, driver development in RTOS or OS Kernel environments, and experience with embedded OSes such as Zephyr, eCos, uC/OS, or FreeRTOS is required. Experience in developing for pre-silicon environments, including simulators and FPGA emulation, is beneficial. Familiarity with ARM v8 architecture and development experience for an ARMV8 platform are also advantageous. As a CPU Performance Management FW Developer, you will have the opportunity to contribute significantly to Qualcomm's cutting-edge technology and play a crucial role in shaping the future of CPU performance management solutions.,

You will be responsible for demonstrating expertise in RTL Coding using Verilog, System Verilog, or VHDL. Your role will involve a strong understanding of FPGA flow, Logic design, and Digital design. It is essential to have knowledge in FPGA architecture and proficiency in Tcl and Python scripting. You will be conducting Vivado testing of synthesis tool and other stages. This position does not entail Silicon RTL development or any HW flow or testing. Your communication skills are crucial, as you will be expected to communicate technical information in an organized and understandable manner. A customer-oriented approach is necessary, along with a demonstrated concern and willingness to assist customers. Good organizational skills, multitasking abilities, prioritization, and activity tracking are essential. Exceptional oral and written communication skills are also required. TekWissen Group is committed to equal employment opportunities and supports workforce diversity.,

Would you like to work in a well-established, highly acclaimed, fast-paced global company located in NOIDA, India Are you a hardworking individual seeking the opportunity to solidify and strengthen your career within an established organization At our organization, we offer a fun and flexible working environment, along with various perks, incentives, and opportunities for further learning and development. We strive to motivate our employees to grow both professionally and personally, encouraging them to excel in their roles and fulfill their potential as the organization expands. Hard work is recognized and rewarded through promotions and other incentives. Here are some reasons to consider joining our team: - Collaborate with supportive leaders who encourage personal development - Enjoy flexible working hours - Access to free snacks and health insurance benefits - Performance incentives and awards to recognize your efforts About Us: Lepide is a global IT security organization with offices in Texas, London, and New Delhi. We lead the data-centric audit and protection market with our award-winning Lepide Data Security Platform. Our mission is to revolutionize how organizations safeguard their unstructured data by focusing on data-centric IT security strategies. With over 1000 customers across 150 countries, we provide enterprise-level insights into data and systems, whether on-premise or in the cloud. We take pride in our unparalleled customer support and our position as the fastest-growing DCAP provider in the market. Roles and Responsibilities: As a member of our team, your responsibilities will include: - Enhancing test case coverage and minimizing customer-reported issues - Identifying code inefficiencies and communicating them effectively to the team - Taking the initiative to propose and implement solutions for code-related challenges - Participating in project planning, time estimation, and documentation tasks - Presenting ideas for system enhancements with cost proposals - Writing detailed specifications and developing program codes - Conducting unit tests to ensure product functionality and GUI quality - Collaborating with quality analysts to address and troubleshoot issues Desired Candidate Profile: We are seeking candidates with the following qualifications and skills: - Proficiency in core development in VC++, MFC (knowledge of DDK, C#, and CLR is a plus) - Strong understanding of Data Structures, Multithreading, Logic Design, and UI/Backend implementation - Familiarity with design patterns and the ability to adapt in a rapidly changing environment - Experience with Active Directory, Group Policy, Windows File Server, and SQL is advantageous - Knowledge of JIRA/Confluence is a plus - Excellent communication skills and the ability to work under pressure and meet deadlines - Experience with Test Driven Development would be beneficial If you believe you align with the qualities and qualifications mentioned above, we encourage you to consider joining our dynamic team.,

Qualcomm India Private Limited is a leading technology innovator that aims to push the boundaries of what's possible and enable next-generation experiences, contributing to the creation of a smarter, connected future for all. As a Qualcomm Hardware Engineer, your responsibilities will involve planning, designing, optimizing, verifying, and testing electronic systems. You will work on a wide range of systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams is a key aspect of the role to develop innovative solutions and meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 6+ years of Hardware Engineering or related work experience. - OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 5+ years of Hardware Engineering or related work experience. - OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 4+ years of Hardware Engineering or related work experience. Preferred Qualifications: - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. - 12+ years of Hardware Engineering or related work experience. - 3+ years of experience in circuit/logic design/validation (e.g., digital, analog, RF). - 3+ years of experience utilizing schematic capture and circuit stimulation software. - 3+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. - 1+ year in a technical leadership role with or without direct reports. Principal Duties and Responsibilities: - Utilize advanced Hardware knowledge to plan, optimize, verify, and test electronic systems. - Implement advanced design rules and processes for electronic hardware, equipment, and integrated circuitry. - Conduct complex simulations and analyses to ensure best power, performance, and area efficiency. - Collaborate with cross-functional teams to implement new requirements and incorporate test solutions to enhance production program efficiency. - Evaluate, characterize, and develop manufacturing solutions for leading edge products. - Provide leadership in the development of complex hardware designs and technical documentation. - Work independently with minimal supervision and provide guidance to team members. Level of Responsibility: - Significant decision-making affecting work beyond immediate work group. - Requires strong verbal and written communication skills. - Moderate influence over key organizational decisions. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you need accommodation during the application/hiring process, please contact Qualcomm. We expect all employees to adhere to applicable policies and procedures, including requirements regarding protection of Company confidential information. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes on our Careers Site.,

SILICON DESIGN ENGINEER 2 THE ROLE: As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence . THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem - solving skills and are willing to learn and ready to take on problems . KEY RESPONSIBILITIES: Drive formal verification for the block and write formal properties and assertions to verify the design Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design Responsible for verification quality metrics like pass rates, code coverage and functional coverage PREFERRED EXPERIENCE: Project level experience with design concepts and RTL implementation for same Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics Good understanding of computer organization/architecture ACADEMIC CREDENTIALS: Bachelor s or M aster s degree in computer engineering/Electrical Engineering #LI-SG

As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This will involve working on a variety of components including yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to bring cutting-edge products to the market. Collaboration with cross-functional teams is a key aspect of this role to ensure that solutions meet performance requirements. The ideal candidate should have a minimum of 4 to 6 years of work experience in ASIC RTL Design. Experience in Logic design, micro-architecture, and RTL coding is essential. Hands-on experience with the design and integration of complex multi clock domain blocks is a must. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols such as AXI, AHB, APB, clocking/reset/debug architecture are also required. Candidates should have experience in Multi Clock designs and Asynchronous interface. Familiarity with ASIC development tools like Lint, CDC, Design compiler, and Primetime is necessary. An understanding of Automotive System Designs, Functional Safety, Memory controller designs, and microprocessors would be advantageous. The role involves close collaboration with Design verification and validation teams for pre/post Silicon debug. Prior experience in Low power design is preferred. Additionally, expertise in Synthesis and a solid grasp of timing concepts for ASIC are must-haves for this position.,

Red Chilli Solutions is seeking experienced technical writers for a full-time contract position with our client, Wipro. The ideal candidate should have over 10 years of experience and be located at Bagmane Tech Park, ORR, Bangalore. Responsibilities: - Create and update technical documentation, including design specifications, user manuals, and system architecture documentation. - Collaborate closely with engineering teams to translate intricate architecture and logic design concepts into clear and understandable content. - Develop diagrams, flowcharts, and other visual aids to enhance documentation. - Ensure all documentation is well-organized, precise, and complies with established standards. Qualifications: - Demonstrated expertise in technical writing with a specialization in architecture and logic design. - Profound understanding of hardware design principles and digital logic. - Exceptional writing, editing, and communication abilities. - Capability to present technical information in a lucid and concise manner. - Proficiency with tools like Markdown, LaTex, or Confluence is advantageous. If you are interested in this opportunity, please forward your resume to nidhi@rcstechwriting.com.,

As a Senior Silicon Verification Engineer at AMD, you will play a crucial role in contributing to the advancement of our cutting-edge technologies. You will be part of a dynamic team focused on delivering high-quality solutions to the market, ensuring AMD remains at the forefront of innovation in the industry. Your dedication and expertise will be instrumental in driving the success of our verification engineering efforts and fostering continuous career growth. Your passion for modern processor architecture, digital design, and verification will be key assets in this role. You will collaborate with a diverse team of engineers across different locations and time zones, leveraging your strong analytical and problem-solving skills to tackle complex challenges. Your ability to communicate effectively and work seamlessly with others will be essential in achieving our collective goals. Key responsibilities in this role include developing and maintaining tests for functional verification at the SOC level, building testbench components to support next-generation IP, and enhancing verification libraries for SOC/full-chip level verification. You will also provide technical support to other teams and assist the hardware emulation team in porting RTL to various platforms. Preferred experience for this position includes familiarity with verification methodologies such as OVM, UVM, or VMM, as well as knowledge of Verilog, logic design concepts, and system-level architecture. Proficiency in UNIX environment and scripting languages like Perl or Python, along with strong waveform debug skills using industry-standard design tools, is highly desirable. Experience with UNIX Revision Control tools, bug tracking tools, and verifying multimillion gate chip designs will be advantageous. To be successful in this role, you should hold a BS/MS in EE, CE, or CS, along with 4+ years of design verification experience and 3+ years of OOP coding experience. Demonstrating excellent communication, presentation skills, and the ability to collaborate effectively with cross-functional teams are essential qualities for this position. Familiarity with processors, boot flow, and software development flow would be beneficial in fulfilling the responsibilities of this role effectively. Join us at AMD and be part of a team that is dedicated to pushing the limits of innovation and transforming lives with groundbreaking technologies. Your contributions will be valued, and your career development will be supported as we work together to advance the future of computing experiences.,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 3 to 15 years of work experience in ASIC/SoC Design Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Excellent oral and written communications skills Proactive, creative, curious, motivated to learn and contribute with good collaboration skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 2-9 years of experience in SoC design Educational Requirements2+ years of experience with a Bachelors/ Masters degree in Electrical engineering Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

AJO / Campaign (Adobe) Role Overview We are seeking a skilled and detail-oriented Adobe Campaign & Journey Orchestration Specialist to lead the implementation and optimization of customer journeys using Adobe Journey Optimizer and Adobe Campaign. This role is critical in delivering personalized, timely, and effective communications across email, push, and SMS channels. Key Responsibilities Journey Implementation & Logic Design Build and maintain orchestrated journeys using Adobe Journey Optimizer and Adobe Campaign. Implement logic for real-time and scheduled delivery using edge-based triggers and behavioural data. Channel Management Manage and optimize delivery across email, push notifications, and SMS. Ensure seamless integration and execution across all outbound communication channels. Experimentation & Personalization Support A/B testing, multivariate testing, and proofing processes to refine personalized offers. Collaborate with analytics and creative teams to iterate on content and targeting strategies. Monitoring & Optimization Monitor delivery logs, KPIs, and performance metrics to identify issues and opportunities. Continuously improve orchestration logic based on data insights and campaign results. Qualifications 3 7+ years Proven experience with Adobe Journey Optimizer and Adobe Campaign (Standard or Classic). Strong understanding of customer journey mapping, segmentation, and personalization strategies. Experience with A/B testing frameworks and campaign proofing. Familiarity with delivery monitoring tools and KPI tracking. Excellent problem-solving skills and attention to detail. Strong communication and collaboration abilities.

Job Description: We are hiring an RTL Design Engineer with hands-on experience in FPGA-based RTL development. This role is focused on FPGA logic design and does not involve Silicon RTL or hardware testing . Key Responsibilities: RTL coding using Verilog, SystemVerilog, or VHDL Work on FPGA architecture and flow , including logic and digital design Scripting with Tcl and Python Perform synthesis and design stages using Vivado Collaborate with design teams to deliver high-quality IP blocks for FPGA

Design of switchgear panel (LV/MV) with Solid Works, AutoCad Knowledge on General/Busbar arrangement + design Design of Modular/bolted/Switchgear panels Design calculations Relevant IS/IEC Handling team, Coordination with Multi Clients & Production Required Candidate profile BE/Dip. in Mech. Skill Solidwork, Autocad 2-4 yrs. in Switchgear panel designing If required needs to travel for client discussions/Drawing approval Knows Tech. Mech. related to Switchgear design

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers.Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLLAdditional responsibilities:logic (RTL) design, timing closure, CDC analysis etc.Understand and Design Power efficient logic.Agile project planning and execution.RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 8+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. . Required education Master's Degree Preferred education High School Diploma/GED Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design,

As a Formal verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Develop skills in IBM Formal verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 – 10 years of relevant industry experience Proven experience in Formal/Functional Verification - Demonstrated execution experience of verification of logic blocks verification. Knowledge of formal methodology, Knowledge of HDLs (Verilog, VHDL, SV), Good programming skills in python, processor core u-arch skills Exposure in developing testbench environment, debugging and triaging fails. Good communication skills and be able to work effectively in a global team environment. Drive verification coverage closure, lead verification team. Drive complex scenarios, participate in High level design discussions. Track record in leading teams. Preferred technical and professional experience Writing test plans, building random / exhaustive formal verification environment, functional and coverage analysis and debug. Good understanding of the Server System

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor core/cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.