Technical Lead

Job Title: SoC Infrastructure Development Lead (Dev-Lead)

Experience: 8+ years
Location: Hyderabad

Notice Period: Immediate to 15 Days

Role Overview

We are looking for a highly experienced and technically strong SoC Infrastructure Development Lead to drive design, integration, and verification of infrastructure IPs that form the backbone of our complex SoC platforms. This role requires deep domain knowledge of infrastructure components such as interconnects, clocks, resets, power domains, debug fabric, and system control blocks, and the ability to coordinate across silicon, firmware, verification, and physical design teams.

Key Responsibilities

SoC Infrastructure Planning and Development

Cross-IP Integration & SoC-Level Ownership

Design Enablement & Firmware Interface

Verification and Validation

Required Expertise

Technical Skills

• Strong RTL design skills using Verilog/SystemVerilog; familiarity with UVM and formal verification flows.
• In-depth knowledge of AMBA (AXI/AHB/APB), NoC, and coherent interconnects (e.g., CCN, CMN, or NOC from Arteris/NVIDIA).
• Expertise in clock tree design, clock gating strategies, and multi-domain reset and power sequencing.
• Experience with RTL-to-GDSII flows, including timing constraints, SDC generation, and ECO handling.

Platform-Specific Expertise

• Experience working on Qualcomm, ARM, Intel, or custom ASIC platforms, with a solid understanding of SoC assembly and platform integration.
• Familiarity with:
• Qualcomm AOSS, RPMh, and RPM message protocol,
• ARM Coresight & debug/mem-ap infrastructure,
• Secure boot, eFuse management, and system control registers,
• DVFS, retention/idle states, and power collapse flows.

Tools & Methodologies

• Proficient with tools like Synopsys Design Compiler, Primetime, VCS, SpyGlass, Questa, or Jasper.
• Working knowledge of scripts in Python/TCL/Perl for automation of flow and register map generation.
• Hands-on experience with hardware-software co-validation platforms (e.g., Synopsys ZeBu, Cadence Palladium, FPGA protos).