Responsibilities: Interface camera modules (e.g., OV7670, OV5640) with FPGA boards Write and simulate System Verilog code for image data acquisition Use MATLAB or Python for processing and visualization of image data Test and debug the camera pipeline from hardware to software Document technical workflow and results Collaborate with team members on weekly progress updates Requirements: Strong understanding of Digital Logic Design Knowledge of FPGA development tools (Vivado, Quartus, etc.) Experience with System Verilog / Verilog HDL Familiarity with MATLAB or Python for data handling and plotting Ability to read camera datasheets and timing specifications Good problem-solving and debugging skills Preferred Qualifications: Final-year or pre-final year students from ECE / EE / CSE Previous experience with image processing or embedded projects is a plus What You’ll Gain: Real-world experience in FPGA-based camera interfacing Exposure to hardware-software integration Certificate, Letter of Recommendation & Portfolio project Potential pathway to long-term roles or R&D positions Job Type: Full-time Pay: From ₹3,000.00 per month Benefits: Flexible schedule Paid sick time Work from home Schedule: Day shift Supplemental Pay: Performance bonus Work Location: In person

Planning, developing and implementing AI (Artificial Intelligence), ML (Machine Learning) algorithms for various medical imaging and signal processing applications using MATLAB/Python/Verilog languages. Writing/Editing/Proof reading/Journal support - Research Documents. Job Type: Full-time Pay: From ₹5,000.00 per month Benefits: Flexible schedule Paid sick time Work from home Schedule: Day shift Supplemental Pay: Performance bonus Work Location: In person

Planning, developing and implementing AI (Artificial Intelligence), ML (Machine Learning) algorithms for various medical imaging and signal processing applications using MATLAB/Python/Verilog languages. Writing/Editing/Proof reading/Journal support - Research Documents. Job Type: Full-time Pay: From ₹5,000.00 per month Benefits: Flexible schedule Paid sick time Work from home Schedule: Day shift Supplemental Pay: Performance bonus Work Location: In person

Responsibilities: Interface camera modules (e.g., OV7670, OV5640) with FPGA boards Write and simulate System Verilog code for image data acquisition Use MATLAB or Python for processing and visualization of image data Test and debug the camera pipeline from hardware to software Document technical workflow and results Collaborate with team members on weekly progress updates Requirements: Strong understanding of Digital Logic Design Knowledge of FPGA development tools (Vivado, Quartus, etc.) Experience with System Verilog / Verilog HDL Familiarity with MATLAB or Python for data handling and plotting Ability to read camera datasheets and timing specifications Good problem-solving and debugging skills Preferred Qualifications: Final-year or pre-final year students from ECE / EE / CSE Previous experience with image processing or embedded projects is a plus What You’ll Gain: Real-world experience in FPGA-based camera interfacing Exposure to hardware-software integration Certificate, Letter of Recommendation & Portfolio project Potential pathway to long-term roles or R&D positions Job Type: Full-time Pay: From ₹3,000.00 per month Benefits: Flexible schedule Paid sick time Work from home Schedule: Day shift Supplemental Pay: Performance bonus Work Location: In person