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Exciting FPGA Roles (6 To 15 Yrs) @ Mirafra Hyderabad

Exciting FPGA Roles (6 To 15 Yrs) @ Mirafra Hyderabad

Mirafra

6 - 11 years

30 - 45 Lacs

Hyderabad

Posted:1 day ago| Platform:

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Skills Required

FPGA Design Vivado Digital Design Debugging

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Full Time

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1)

Strong in digital design. • Strong in Xilinx Vivado IP & IPI tools till bit-generation. • Knowledge of VHDL/Verilog/System Verilog. • Knowledge of Validating IP/IP Example designs on Xilinx boards, debugging of failures on target boards, board bring up. • Proficiency in Linux environment. • Good communication skills. Basic Job Deliverable : RTL coding, IP design, Modify/update existing IP as per requirements.

2)

7 to 12 years of experience in digital design.
• RTL coding experience using Verilog and/or System Verilog.• Working experience of AMD/Xilinx FPGA and Vivado.• Experience in Video domain (DisplayPort/MIPI) is preferred.• Candidate shall be working at AMD Sattva site, Hyderabad.

Design Creation and Analysis profile with RTL, STA, Scripting and FPGA flow (Vivado/ Quartus/ Lattice).

Education & Other Requirements

B.Tech / M.Tech / BE in Electronics, Electrical, ECE or equivalent

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