Vlsi Design Engineer

Role & responsibilities

Must Have:

SV/UVM

Test Bentch Developement

Any Protocols:

(PCI Express or UCIe, CXL or NVM

• AXI, ACE or CHI
• Ethernet, RoCE or RDMA
• DDR or LPDDR or HBM)

• 8+ years of hands-on DV experience in System Verilog/UVM.
• Must be able to own and drive the verification of a block / subsystem or a SOC.
• Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM.
• Must have extensive experience in verification of one or more of the following:
• PCI Express or UCIe, CXL or NVM
• AXI, ACE or CHI
• Ethernet, RoCE or RDMA
• DDR or LPDDR or HBM
• ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages
• Power Aware Simulations using UPF

Role : ASIC RTL Engineer / Digital Design

Exp : 7 +

Mandatory Skill :

• RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory
• PCIe/DDR/Ethernet - Any One
• I2C,UART/SPI - Any One
• Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One
• Scripting languages like Make flow, Perl ,shell, python - Any One

Good to have :

• processor architecture / ARM debug architecture
• debug issues for multiple subsystems
• create/review design documents for multiple subsystems
• Able to support physical design, verification, DFT and SW teams on design queries and reviews

Details JD :

Expertise in SoC subsystem/IP design

Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog

In depth knowledge on RTL quality checks (Lint, CDC)

Knowledge of synthesis and low power is a plus

Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)

Good understanding of timing concepts

Knowledge of one or more of the interface protocols

a. PCIe

b. DDR

c. Ethernet

d. I2C, UART, SPI

Expertise in setting up and using tools like

a. Spyglass Lint/CDC

b. Synopsys DC

c. Verdi/Xcellium

Understanding of scripting languages like Make flow, Perl ,shell, python etc

Understanding of processor architecture and/or ARM debug architecture is a plus

Able to help and debug issues for multiple subsystems

Able to create/review design documents for multiple subsystems

Able to support physical design, verification, DFT and SW teams on design queries and reviews