675 Systemverilog Jobs - Page 12

Location – Noida, Hyderabad: AMS Layout Engineers – 4 Positions AMS Design / Verification / Layout Engineers – 8 Positions Experience: 4 to 10 Years Job Type: Full-time (On-site) Notice Period: Immediate to 30 Days preferred Role Categories AMS Design Engineer Experience in Analog and Mixed Signal circuit design Strong understanding of CMOS, PLLs, ADCs, DACs, LDOs, Oscillators, and Power Management blocks AMS Verification Engineer Hands-on experience in AMS simulation techniques using Verilog-AMS or SystemVerilog-AMS Good exposure to mixed-signal testbench development and verification methodology AMS Layout Engineer Deep knowledge of analog/mixed-signal layout including matching, shielding, floor planning, and DRC/LVS checks Experience with layout tools such as Virtuoso, Calibre, etc. Desired Skills Solid understanding of analog and mixed-signal concepts Proficiency with industry-standard EDA tools (Cadence Virtuoso, Spectre, Calibre, etc.) Prior experience in tape-outs at advanced technology nodes (28nm and below is a plus) Strong communication and collaboration skills Skills: systemverilog-ams,shielding,ams design,power management blocks,dacs,drc,adcs,floor planning,matching,ams simulation techniques,layout,signal,drc/lvs checks,layout tools,power management,analog and mixed signal circuit design,verilog-ams,spectre,ldos,ams layout,ams verification,virtuoso,design,mixed-signal testbench development,calibre,oscillators,cadence,cmos,plls,cadence virtuoso,lvs,analog/mixed-signal layout

Location – Noida, Hyderabad: AMS Layout Engineers – 4 Positions AMS Design / Verification / Layout Engineers – 8 Positions Experience: 4 to 10 Years Job Type: Full-time (On-site) Notice Period: Immediate to 30 Days preferred Role Categories AMS Design Engineer Experience in Analog and Mixed Signal circuit design Strong understanding of CMOS, PLLs, ADCs, DACs, LDOs, Oscillators, and Power Management blocks AMS Verification Engineer Hands-on experience in AMS simulation techniques using Verilog-AMS or SystemVerilog-AMS Good exposure to mixed-signal testbench development and verification methodology AMS Layout Engineer Deep knowledge of analog/mixed-signal layout including matching, shielding, floor planning, and DRC/LVS checks Experience with layout tools such as Virtuoso, Calibre, etc. Desired Skills Solid understanding of analog and mixed-signal concepts Proficiency with industry-standard EDA tools (Cadence Virtuoso, Spectre, Calibre, etc.) Prior experience in tape-outs at advanced technology nodes (28nm and below is a plus) Strong communication and collaboration skills Skills: systemverilog-ams,shielding,ams design,power management blocks,dacs,drc,adcs,floor planning,matching,ams simulation techniques,layout,signal,drc/lvs checks,layout tools,power management,analog and mixed signal circuit design,verilog-ams,spectre,ldos,ams layout,ams verification,virtuoso,design,mixed-signal testbench development,calibre,oscillators,cadence,cmos,plls,cadence virtuoso,lvs,analog/mixed-signal layout

Category Engineering Hire Type Employee Job ID 12140 Remote Eligible No Date Posted 13/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and motivated ASIC Digital Design Engineer with a relentless passion for innovation and a commitment to excellence. Your deep expertise in digital design and verification is matched by your curiosity and willingness to tackle complex challenges. You have a solid foundation in microprocessor architectures and are adept at developing and maintaining hardware-software co-simulation environments. Your analytical mindset enables you to create comprehensive functional and code coverage models, and you handle regression testing with precision and care. Your technical toolkit is robust: you are fluent in HDL and verification languages such as SystemVerilog and Verilog, and you bring strong programming skills in C, C++, assembly, Python, and Perl. You are comfortable using RTL simulators and verification tools and are always eager to expand your technical horizons by learning new methodologies. Collaboration is second nature to you—you thrive in multi-cultural, multi-time zone teams and foster inclusive teamwork. Your excellent communication skills ensure that your ideas are heard and understood, and you enjoy sharing your knowledge while learning from others. You take pride in delivering high-quality, reliable work, and you are driven by the opportunity to make a meaningful impact on the future of technology. What You’ll Be Doing: Developing and automating advanced testbenches for ARC processor verification processes. Creating and maintaining functional coverage models and analyzing coverage reports for completeness and effectiveness. Performing comprehensive code coverage analysis to ensure thorough verification and identify potential gaps. Integrating both third-party and internal verification IPs into verification environments. Managing regression testing cycles, analyzing results, and ensuring robust test coverage across all features. Collaborating with multi-site and multi-cultural teams to drive next-generation ARC processor verification projects. Contributing to the improvement of verification methodologies and automation flows. The Impact You Will Have: Ensuring the reliability and high performance of next-generation ARC-V processors. Contributing to the delivery of cutting-edge silicon IP solutions that power industry-leading products. Enhancing the efficiency and effectiveness of verification techniques and processes. Reducing time-to-market for high-performance, low-risk products through rigorous verification. Championing collaboration and knowledge sharing across global engineering teams. Helping Synopsys maintain and strengthen its leadership position in the semiconductor industry. What You’ll Need: Bachelor’s degree in engineering or a related technical field (required). 4+ years of experience in digital design and verification, with a proven track record of success. Strong knowledge of digital design principles and methodologies. Proficiency in SystemVerilog, Verilog, C, C++, assembly, Python, and Perl. Hands-on experience with RTL simulators and verification tools. Experience with microprocessor architectures (RISC-V experience is a significant plus). Who You Are: An excellent communicator with strong verbal and written skills. A collaborative team player who thrives in a multi-cultural, multi-time zone environment. Analytically minded with exceptional problem-solving skills and attention to detail. Adaptable and eager to learn new technologies, tools, and methodologies. Self-driven, proactive, and passionate about delivering high-quality, reliable results. The Team You’ll Be A Part Of: You will be a key member of the Synopsys DesignWare ARC Processor hardware team, working alongside talented engineers on next-generation ARC processor verification. The team is dedicated to developing and maintaining advanced verification environments, ensuring the high performance and reliability of our silicon IP solutions. You will collaborate with colleagues across various locations and time zones, contributing to innovative projects that drive the semiconductor industry forward. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Key Responsibilities: Develop AMS verification environments from the ground up using SystemVerilog/UVM Own and execute test planning, AMS setup, and mixed-signal simulation Work on SerDes verification involving high-speed protocols (PCIe, USB 3.0, MIPI, etc.) Model and verify analog/mixed-signal blocks using wreal , RNM , and Verilog-A Perform simulations using VCS Primesim AMS and Primesim XA tools Collaborate closely with analog, digital, and system teams for integrated AMS verification

Key Responsibilities: Hands-on microarchitecture and RTL development for IP blocks Develop microarchitecture based on design specifications, including HW-SW interface definition IP-level verification and debugging for video and audio subsystems Work on MIPI CSI and DSI protocols understanding at protocol and implementation level Collaborate with design, verification, and software teams to ensure high-quality deliverables Drive or contribute to test plan creation, environment development, and coverage closure

Job Description: We are looking for an experienced SoC DV Lead with a strong background in SoC verification and hands-on experience in writing C test cases for SoC-level DV. Key Responsibilities: Lead SoC DV activities from planning to closure Develop and debug C-based test cases for system-level verification Work closely with design, architecture, and firmware teams Perform coverage analysis and ensure comprehensive validation Guide and mentor junior DV engineers Key Skills: SoC-level design verification C programming for test development Debugging and problem-solving Exposure to UVM/SystemVerilog (preferred) Strong understanding of SoC architecture

Location Karnataka Bengaluru Experience Range 8 - 10 Years Job Description Senior IO-MMU Verification Engineer Role Overview: Responsible for functional verification of IO-MMU units, focusing on translation, protection, and system interaction with DMA/IP blocks. Key Responsibilities: Develop UVM-based environments for IO-MMU verification Create tests for virtual address translation, permissions, and fault injection Verify compliance with protocols like PCIe ATS, PRI, and ARM SMMU Collaborate with SoC-level teams for system integration and validation Drive functional and code coverage closure Required Skills: 8+ years in verification of memory or IO subsystems Expertise in UVM, SystemVerilog, SVA Strong debugging and protocol knowledge (AXI, PCIe, SMMU) Experience with constrained-random and assertion-based verification Familiar with trace analysis and formal verification integration

Location Karnataka Bengaluru Experience Range 8 - 10 Years Job Description Senior IO-MMU Design Engineer Role Overview: Leads the design and integration of IO Memory Management Units (IO-MMUs) for secure, virtualized, and high-performance SoC architectures. Key Responsibilities: Architect and implement RTL for IO-MMU subsystems Define IO translation and access control logic Collaborate with SoC, interconnect, and virtual memory teams Ensure compliance with IOMMU standards (SMMU, PCIe ATS/PRI, RMRR) Deliver Lint, CDC, synthesis, and DFT clean designs Required Skills: 8+ years of experience in SoC and IP-level RTL design Strong in SystemVerilog, with knowledge of memory protection and address translation Experience with SoC virtual memory systems and PCIe/AXI protocols Familiar with coherency, TLB, page walk and IOVA mechanisms Skilled in timing closure and formal/CDC tools

As an AMS Verification Engineer, you will play a crucial role in ensuring the successful verification of Analog Mixed Signal designs. With a minimum of 5 years of experience in this field, you will be responsible for developing and executing verification plans, creating testbenches, and collaborating with design teams to guarantee that designs meet specifications. Your key skills will include strong RNM modeling proficiency, hands-on experience with Cadence AMS/DMS flow, familiarity with SystemVerilog and Verilog-AMS, and a solid understanding of analog and mixed-signal design principles. Additionally, you should have expertise in UVM, the ability to debug AMS modeling issues, and experience with basic scripting and automation. Your responsibilities will involve building and maintaining SystemVerilog real number models, verifying AMS/DMS IP/chip functionality, and ensuring effective communication and documentation throughout the verification process. By working closely with both analog and digital design teams, you will contribute to the successful verification of complex AMS designs. If you are a detail-oriented verification engineer with a passion for analog mixed-signal design and a strong background in AMS verification, this role offers an exciting opportunity to further your career in a dynamic and collaborative environment.,

Experience: 5 Years Location: Bangalore/Hyderabad Education: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/Electronics Roles and Responsibilities DDR Verification: Lead the verification of DDR memory controller and PHY designs, ensuring compliance with DDR standards such as DDR3, DDR4, DDR5, and other memory interface protocols. Testbench Development: Develop and implement scalable, reusable, and efficient verification environments and testbenches for DDR designs using SystemVerilog, UVM (Universal Verification Methodology), and other industry-standard verification methodologies. Protocol Compliance: Ensure the DDR design meets protocol specifications, including command, data, and clock synchronization, read/write cycles, burst transfers, refresh cycles, error handling, and power management. Verification Plan Creation: Develop detailed verification plans based on DDR specifications and requirements, ensuring full coverage of corner cases, timing, and protocol validation. Simulation & Debugging: Run simulations and debug issues using tools such as Questa, VCS, or ModelSim, applying advanced debugging techniques such as waveform analysis, assertion-based verification, and code coverage. Regression Testing: Set up and manage regression testing for DDR functionality to ensure continuous validation and early detection of design issues. Verification Coverage: Achieve high functional and protocol coverage, ensuring that critical aspects of DDR design, including timing constraints, corner cases, and failure scenarios, are thoroughly verified. Formal Verification: Implement formal verification techniques to validate key components of the DDR design, ensuring correctness in timing and data flow, and verifying the most critical operations.

Job Description: We are seeking a skilled professional with expertise in design and validation to join our dynamic and innovative team. The ideal candidate will have a strong background in developing and validating FPGA-based solutions, along with solid knowledge of PCIe, CXL, USB and other protocols. We are looking for someone who is enthusiastic about tackling daily technical challenges, self-motivated, proactive, responsive, persistent, and outstanding in problem-solving. Key Responsibilities: Develop and implement comprehensive validation plans for PCIe, CXL, USB and other interface solutions, ensuring compliance with industry standards and specifications. Design FPGA-based solutions to support Hardware Assisted Verification (HAV). Perform thorough testing and validation of solutions, proactively identifying and resolving issues. Collaborate with design teams to understand architecture and requirements, providing constructive feedback to improve product quality. Document validation processes, results, and key insights, delivering clear and concise reports to stakeholders. Work closely with cross-functional teams to ensure seamless project execution. Stay current with industry trends and advancements in validation methodologies and tools. Qualifications: Bachelor’s or Master’s degree in Electronics, Electrical, or Computer Engineering (or a related field), with at least 8 years of design and validation experience. Extensive knowledge of FPGA-based design and validation methodologies. Strong understanding of high-speed protocols such as PCIe, CXL, and USB. Proficiency in programming languages including C/C++, SystemVerilog, Verilog, Perl, Python, and TCL. Experience with emulation or prototyping platforms (e.g., ZeBu, HAPS) is a plus. Excellent problem-solving skills and keen attention to detail. Strong communication and collaboration abilities, with a proven track record of effective teamwork.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the Digital Low Power IPs for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle (including Functional, Low Power Verification, Gate Simulation, Formal Verification) from system-level concept to tape out and post-silicon support. Responsibilities: Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful IP level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications: Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. 8+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications: Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as Power Management Flows, PCIe, USB, MIPI, LPDDR, etc. will be a value add Experience in scripting languages (Python, or Perl). Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075495

About This Opportunity We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What You Will Do Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. You will bring Key Responsibilities: Lead a team of verification engineers, providing mentorship and guidance to ensure efficient and reusable verification practices. Collect and address, team status and metrics. Take full responsibility for the verification strategies that the team has responsibility for. Define and implement UVM-based test environments. Break down requirements to create a Verification Strategy and develop and execute a Verification Plan. Develop, run, and debug test cases to ensure design quality. Continuously improve and optimize verification methodologies. Generate comprehensive documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Develop competence in the technical domain. Foster cross-team collaboration to ensure seamless project delivery and integration. Required Qualifications: Bachelor’s degree in electrical or computer engineering. 8+ years of industry experience in verification using SystemVerilog and UVM. Proven track record of leading verification test plan development in cross-site environments. Proficiency in/with: architecting and creating new grounds-up random and directed test environments and testcase strategies. formal verification for connectivity checks and using assertion-based VIPs. architecting and leading implementation of scoreboards, checkers, bus functional models SystemVerilog Assertions. Strong experience in low-power design verification. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more. Primary country and city: India (IN) || Bangalore Req ID: 766878

Talented and motivated Mid-Level CPU Subsystem Design and Verification Engineer to join our growing team. Responsibilities : Design : Participate in the design of CPU subsystems, collaborating with architects and design engineers. Contribute to micro-architectural decisions, considering performance, power, and area trade-offs. Develop detailed design documents and schematics for assigned subsystems. Verification : Develop comprehensive test plans and verification strategies for assigned subsystems. Create and implement SystemVerilog/UVM testbenches, checkers, and coverage groups. Execute verification plans, analyse results, and debug failures effectively. Work closely with verification engineers and architects to identify and resolve issues. Additional Responsibilities: Stay up-to-date on the latest advancements in CPU architecture and verification methodologies. Contribute to technical discussions and actively participate in design reviews. Collaborate effectively with cross-functional teams to achieve project goals. Qualifications : Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. 3-5 years of experience in CPU design or verification. Strong understanding of digital design principles, RTL, and verification methodologies (UVM, SystemVerilog). Experience with Verilog/SystemVerilog coding and debugging. Familiarity with CPU microarchitecture concepts and verification best practices. Excellent analytical and problem-solving skills. Strong communication and collaboration skills. Ability to work independently and as part of a team. Benefits : Competitive salary and benefits package. Opportunity to work on cutting-edge technology and make a real impact. Regards, K Himabindu Mail Id: himabindu.jeevarathnam@acldigital.com

Hi Folks ACL Digital is Hiring! Experience: 4 - 5+ Years Location: Bangalore / Hyderabad Looking: Immediate to 20 days Hiring | RTL Design Engineer Strong experience in RTL Design using Verilog/System Verilog Exposure to complex SoC/ASIC design and integration Hands-on with synthesis, Lint, CDC preferred Share resume at himabindu.jeevarathnam@acldigital.com #RTLEngineer #ACLdigital #VLSIJobs #ASICDesign #Verilog #SystemVerilog #SoC Thanks, K Himabindu

As a Verification Engineer at Google, you will play a crucial role in ensuring the functionality and performance of Google's custom silicon solutions. You will be responsible for verifying digital systems, including infrastructure IP, interconnects, caches, memory management, and system services. Your expertise will be instrumental in shaping the next generation of hardware experiences, delivering unmatched performance, efficiency, and integration. Your responsibilities will include planning and executing the verification of configurable Infrastructure IPs, interconnects, and memory subsystems. You will develop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM). Additionally, you will create cross-language tools and scalable verification methodologies to ensure comprehensive testing coverage. To excel in this role, you should have a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. You should possess experience in verifying digital systems using standard IP components/interconnects, such as microprocessor cores and hierarchical memory subsystems. Proficiency in Design Verification Test, SystemVerilog, Verilog, Computer Architecture, System On a Chip, C, C++, and Python is required. Experience in creating and using verification components and environments in standard verification methodology, scripting languages, and software development frameworks is essential. Preferred qualifications for this position include a Master's degree or PhD in Electrical Engineering or Computer Science, along with 3 years of experience in areas such as Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, or Clock and Power Controllers. Experience with building verification methodologies spanning simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes is advantageous. Knowledge of Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL), performance verification of SOCs, pre-Silicon analysis, and post-Silicon correlation is also beneficial. Join our team at Google and be part of the innovation that drives the future of direct-to-consumer products. Your contributions will have a global impact, shaping products loved by millions worldwide. Embrace the opportunity to work on the verification of Google's System on a Chip (SOC) offerings, collaborating with hardware architects and design engineers to deliver cutting-edge hardware experiences. Your role will involve developing performance Virtual IP address (VIPs) for supported protocols, deploying verification stacks across diverse IPs, and building generalized system topology abstractions. Together, we will develop methodologies and tools to tackle complex challenges and advance technology for the betterment of society.,

Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Formal Verification to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer, you will be part of a team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook’s data center applications. You will be developing comprehensive formal testplans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. ASIC Engineer, Formal Verification Responsibilities: Propose, implement and promote the Formal Verification Methodology to be used across the group, both at the top level and at the block level Work with Architecture and Design teams to come up with Formal Verification specification and implementation Define Formal Verification scope, create Formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level Build reusable/scalable environments for Formal Verification and deploying tools Evaluate and recommend EDA solutions for Formal Verification Provide training for internal teams and mentoring engineers related to Formal Verification Technology Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 7+ years of experience in Formal Verification Experience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc. Experience with Formal Verification methodologies, complexity reduction techniques and abstraction techniques Experience using analytical skills to craft novel solutions to tackle industry-level complex designs Demonstrated experience with effective collaboration with cross functional teams Fluency in hardware description languages, such as SystemVerilog and SVA Proficiency in scripting languages such as Python, Perl, or Tcl Experience with JasperGold or VC-Formal Preferred Qualifications: Experience to quickly understand and interpret specifications and extract design behaviors/properties Experience in formal property verification of complex compute blocks like DSP, CPU, GPU or HW accelerators Experience with complex SoCs Formal verification experience in clock domain crossing, IP-XACT based register verification and low power Experience with development of fully automated flows from specification to fully verified designs Experience with simulators and waveform debugging tools About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

IPrincipal P/RTL Design Engineer for ARM CMN Fabric and Neoverse Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Principal IP/RTL Design Engineer for ARM CMN Fabric and Neoverse Position Overview Seeking an IP/RTL Design Engineer with 10+ years of experience to design IP/RTL for ARM Neoverse-based SoCs, focusing on CMN fabric, using Socrates for configuration, targeting AI/HPC datacenter applications. Key Responsibilities Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect. Develop Verilog/SystemVerilog RTL for high-performance, low-latency designs. Configure CMN topologies using Arm Socrates for optimized performance and scalability. Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects. Optimize designs for bandwidth, latency, and power in AI/HPC workloads. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS/PhD in Electronics/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics (e.g., CMN-600/700/S3). Skills: Expert in Verilog/SystemVerilog RTL design. Deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects. Deep understanding in system architecture, coherence and cache Experience with Arm Socrates for CMN configuration. Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols. Familiarity with synthesis and timing tools (e.g., Synopsys Design Compiler). Experience with AI/HPC or datacenter SoC design. Knowledge of DDR5, HBM3, or chiplet-based architectures. Familiarity with UALink or Ultra Ethernet. Strong problem-solving and collaboration skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for TPU Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for TPU Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for Ethernet Switch Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Position Overview IP/RTL Design Engineer for Ethernet Switch Position Overview We are seeking an experienced IP/RTL Design Engineer with over 10 years of experience to join our team in designing and developing intellectual property (IP) and RTL for Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches. Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals. Optimize designs for low latency, high throughput, and power efficiency. Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation. Use P4 or related languages for programmable packet processing. Collaborate with teams for synthesis, timing closure, and IP integration. Document designs and stay updated on AI networking trends. Required Qualifications Education: BS/MS/PhD in Electrical or Computer Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Familiarity with power optimization or SDN. Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools. Soft Skills: Strong problem-solving, communication, and teamwork skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SE NIOR SILICON DESIGN ENGINEER KEY RESPONSIBILITIES: Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware Collaborate with cross teams to integrate models into AMD tools used for system-level designs, ensuring proper functionality and performance Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging Create clear and comprehensive documentation for models, including usage guidelines and design specifications. Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges is a plus Version control systems such as Perforce, ICManage or Git PREFERRED EXPERIENCE: B.E/M.E/M.Tech or B.S/M.S in EE/CE with 5+ years of relevant experience in SystemC modelling Proven experience in SystemC and TLM2 modeling Strong understanding of memory controller architectures, including DDR, LPDDR, and other relevant standards Proficiency in C/C++ programming UVM Verification Experience Strong verbal and written communication skills Should have experience working in geographically dispersed team and should be a strong team player ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. Perform design optimizations for area, power, and performance. Conduct design reviews and ensure compliance with coding standards and best practices. Work closely with verification teams to develop test plans and ensure 100% functional coverage. Debug and resolve design and integration issues during simulation and post-silicon validation. Participate in timing analysis and closure in collaboration with the physical design team. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2-10 years of experience in RTL design and implementation for VLSI systems. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. Experience in static timing analysis (STA) and timing closure workflows. Strong problem-solving skills and the ability to debug complex design issues. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: Experience with low-power design and multi-clock domain systems. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. Familiarity with machine learning or AI-based RTL optimizations. Why Join Us Work on groundbreaking projects in VLSI design and technology. Collaborate with a team of industry experts in a supportive and innovative environment. Opportunities for career growth and continuous learning. Competitive salary and benefits. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of analog design!,

Siemens EDA is a global technology leader in Electronic Design Automation software, enabling companies worldwide to develop innovative electronic products efficiently. Customers utilize our tools to advance technology and physics boundaries for superior products in chip, board, and system design. Join the Questa Simulation Product core R&D team based in Noida, working on various simulation verticals with a dynamic and motivated group. The role may involve travel to different locations, offering opportunities to collaborate on impactful projects globally. As a software engineer in the QuestaSim R&D team, you will be responsible for core algorithmic advancements, software design, and architecture. Collaborate with senior software engineers to enhance new components, algorithms, and engines while maintaining production-quality code. Self-motivation, goal-setting, and consistent work in a dynamic environment are keys to success in this role. Qualifications: - B.Tech or M.Tech in CSE, EE, or ECE from a reputable institution with 12+ years of experience. - Proficiency in C/C++, algorithms, data structures, compiler concepts, and optimizations. - Knowledge of UNIX/Linux platforms. - Strong problem-solving and analytical skills. - Ability to work independently and lead project teams. Desirable Skills: - Understanding of digital electronics concepts. - Familiarity with ML, AI algorithms, Verilog, SystemVerilog, VHDL, parallel algorithms, and job distribution techniques. - Experience in simulation or formal verification methodologies. Join Siemens, a global team of over 377,000 minds shaping the future across 200+ countries. We value diversity and encourage applications reflecting the communities we serve. Employment decisions are based on qualifications, merit, and business requirements. Bring your creativity and curiosity to help build tomorrow's innovations. Transform the everyday with Siemens EDA.,

As a Siemens EDA ambassador, you will play a crucial role in the fast-evolving electronics industry by empowering customers to introduce groundbreaking innovations to the market swiftly and attain leadership in their respective sectors. Siemens EDA is committed to providing a comprehensive range of electronic design automation (EDA) software, hardware, and services on a global scale to achieve this goal. Your primary responsibilities will involve spearheading the design, development, and implementation of software solutions for both internal and external products. It is essential to ensure that the delivered solutions not only meet but exceed customer expectations while maintaining the highest quality standards. Your role will be instrumental in ensuring the functional excellence of released products across various platforms, addressing intricate challenges proactively. Additionally, you will be accountable for devising and executing software designs that span multiple product domains, collaborating seamlessly with cross-functional teams to enhance efficiency, boost performance, and elevate our solutions. To qualify for this role, we are seeking individuals with a B.E./B.Tech./M.Tech. degree in Computer Science, Electrical Engineering, Electronics & Communication, Instrumentation & Control, or related fields. You should have 3-5 years of experience in software development, with a specific focus on FPGA synthesis solutions. Proficiency in digital design fundamentals, C/C++, and Object-Oriented Programming (OOP) is essential. A strong aptitude for algorithm analysis, development, and optimization of data structures is crucial, coupled with a commitment to continuous improvement through open and constructive feedback. Having familiarity with synthesis, simulation, and verification methodologies would be advantageous for this role. Moreover, a basic understanding of at least one Hardware Description Language (HDL) such as Verilog, SystemVerilog, VHDL, or SystemC is highly beneficial. This position is based in Noida, offering you the opportunity to collaborate with diverse teams, contribute to shaping the future, driving innovation, and delivering cutting-edge solutions. Siemens is a global organization comprising over 377,000 talented individuals working across 200 countries. We are dedicated to promoting diversity and equality in the workplace, and we value applications that reflect the communities in which we operate. Employment decisions at Siemens are merit-based and driven by qualifications and business requirements. Join us with your curiosity and creativity to help shape a better tomorrow! In return, we provide a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare benefits. If you are passionate about transforming the ordinary into extraordinary and want to be part of a dynamic team committed to innovation, then this role at Siemens EDA is the perfect opportunity for you.,

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER KEY RESPONSIBILITIES: Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware Collaborate with cross teams to integrate models into AMD tools used for system-level designs, ensuring proper functionality and performance Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging Create clear and comprehensive documentation for models, including usage guidelines and design specifications. Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges is a plus Version control systems such as Perforce, ICManage or Git PREFERRED EXPERIENCE: B.E/M.E/M.Tech or B.S/M.S in EE/CE with 5+ years of relevant experience in SystemC modelling Proven experience in SystemC and TLM2 modeling Strong understanding of memory controller architectures, including DDR, LPDDR, and other relevant standards Proficiency in C/C++ programming UVM Verification Experience Strong verbal and written communication skills Should have experience working in geographically dispersed team and should be a strong team player ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.