Verification Engineer

Your role as a Verification Engineer will involve developing comprehensive verification plans and strategies for SoC and GLS components. You will design, implement, and maintain reusable testbenches using SystemVerilog and UVM methodologies. Additionally, you will be responsible for performing functional verification of AMBA bus protocols including AXI, AHB, and APB. Collaboration with RTL designers and architects to understand specifications and implement verification environments accordingly is key. Analyzing verification results, debugging issues, and providing timely resolutions to meet project timelines will be part of your daily tasks. Ensuring coverage goals are met through simulation and formal verification techniques is crucial. Optionally, you may participate in DSP module verification to enhance verification scope. Furthermore, mentoring junior engineers and contributing to process improvements within the verification team will be expected from you. Your qualifications should include 5 to 10 years of experience in SoC and GLS verification in a semiconductor environment. You must possess strong proficiency in SystemVerilog, UVM, and C programming for verification purposes. Extensive experience with AMBA protocols (AXI, AHB, APB) and bus functional modeling is necessary. While a good understanding of DSP modules and verification is preferred, it is not mandatory. Experience with simulation tools like Questa, VCS, or similar is required. Strong analytical, debugging, and problem-solving skills are essential. Excellent communication and teamwork skills are vital, with the ability to work effectively in a collaborative environment. A Bachelors or Masters degree in Electronics, Computer Science, or related engineering discipline is a prerequisite. The company details were not provided in the job description.,