Silicon Design Verification Engineer

Intel

3 - 6 years

14 - 19 Lacs

bengaluru

Posted:3 days ago| Platform:

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Skills Required

data validation linux verilog hdl unix soc verification physical design c++ soc simulation design verification graphics sub-system axi solid works product development coloring ahb system verilog asic asic verification ovm rtl uvm spi dfmea pcie

Work Mode

Work from Office

Job Type

Full Time

Job Description

Performs functional logic verification of an integrated SoC to ensure design will meet specifications.
Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment.
Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
Maintains and improves existing functional verification infrastructure and methodology.
Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.

Qualifications:

Must have either a BS + 15 years' experience or MS + 13 years' experience in Computer Science, Computer Engineering or Electrical Engineering.Minimum 10 years' experience working on Validation, verification, or integration using Verilog/System Verilog.
Minimum 13 years' experience with writing validation plans and software to implement those validation plans.
Minimum 8 years' experience with an object-oriented programming language. Minimum 8 years' experience with Verilog or other HDL.
Minimum 5 years' experience with UNIX or Linux.

Required Skill -

Minimum 14 years with validation experience.
Exposure to Graphics/Media/Display/SOC Security features is highly desired with strong expertise in any of these domains.

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