477 Rtl Coding Jobs - Page 9

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: We are seeking a highly skilled and experienced Sub-System Hardware Architect specializing in ASIC design for AI to join our dynamic team. The ideal candidate will have a strong background in hardware design and architecture, with a focus on AI sub-systems. This role involves defining and leading the hardware architecture for ASIC components within the Turing subsystem, ensuring they meet performance, reliability, power, and scalability requirements. Desired Skillset: Proven experience in designing and developing ASIC sub-system hardware components for AI applications. Strong knowledge of ASIC design tools and methodologies. Excellent problem-solving and analytical skills. Ability to work effectively in a team environment. Strong communication and interpersonal skills. Expertise in writing detailed hardware specifications and good documentation practices. Knowledge of micro-architecture, RTL coding, and clock controller design. Strong understanding of low power designs and strategies. Excellent written and verbal communication skills. Minimum Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 8 to 12 years of experience in ASIC design and architecture. Principal Duties and Responsibilities: Define sub-system hardware architecture, covering performance, power strategies, etc. Collaborate with cross-functional teams, including Product, Software, SOC, and Hardware Implementation teams, to define hardware requirements and specifications. Develop and implement ASIC hardware architecture strategies for AI. Conduct power assessment and set power targets as part of the architecture work. Conduct studies to improve performance and identify bottlenecks. Write detailed and precise hardware specifications and maintain thorough documentation. Conduct feasibility studies and risk assessments for ASIC designs. Perform detailed analysis and optimization of ASIC hardware performance. Provide technical guidance and mentorship to junior engineers. Stay updated with the latest advancements in ASIC technology and AI applications. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years’ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Place and Route. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Verification. Experience1-3 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: Embedded and System Software. Experience3-5 Years.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Required technical and professional expertise . 6 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running.The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise Join Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, weve united two industry leaders to create an optical networking powerhousecombining cutting-edge technology with proven leadership to redefine the future of connectivity. Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. As an FPGA Verification engineer, you will be responsible for designing verification plans, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product. Candidate should be capable of handling projects independently and have a strong will to drive for solutions. Must have 12 16 yearsof experience in developing System Verilog UVM based test environments, developing and implementing test plans at block, sub-chip and chip levels. Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform-based debugging tools. Exposure to UVM (or similar) verification methodologies is required. Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred. Should be conversant with technologies like the Ethernet, PCIe, I2C, SPI etc. Knowledge of telecom protocol is preferred. Structured and thorough with analytical and troubleshooting skills. Good written and oral communication skills are required. Flexible, innovative, self-driven and willing to take initiatives. Highly motivated team player with exceptional leadership capability. Develop and execute verification plans for high-complexity DWDM systems used in LH/ULH optical network applications. Design and implement simulation environments and testbenches to validate FPGA functionality and performance. Create and run functional and directed/random test scenarios to ensure comprehensive design coverage. Perform detailed coverage analysis and implement strategies to achieve full functional and code coverage. Collaborate closely with cross-functional R&D teams across multiple global locations throughout the product lifecycle. Provide lab support during board bring-up and assist in root cause analysis to ensure first-time-right product quality. Independently manage verification projects with a proactive and solution-driven approach to meet quality and timeline goals.

Key Responsibilities : Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption. Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designs Architect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores). Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques. Develop and refine RTL code in Verilog/SystemVerilog for ASIC development. Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design. Perform RTL design reviews, debugging, and optimization to meet design targets such as area, speed, and power. Work on creating micro-architectural specifications and ensure the design meets project requirements. Ensure designs are implemented with proper synchronization, timing constraints, and low power techniques. Participate in top-level design, integrating IP blocks, ensuring design consistency across subsystems. Drive the design flow from architecture and specifications through to implementation. Prepare and maintain technical documentation for designs and related processes. CDC, LINT and Integration expertise is expected. Required Skills & Experience : Bachelor's, Master's, or PhD in Electrical Engineering or related fields. 3-12 years of experience in RTL design for ASICs, with at least 3 years in a team lead role. Expertise in RTL design using Verilog or System Verilog. Solid understanding of digital design principles, including timing analysis, state machines, and pipelining. In-depth knowledge of ASIC design flow, from RTL to tape-out. Experience with EDA tools for synthesis, simulation, and timing analysis (e.g., Synopsys, Cadence). Strong debugging and problem-solving skills. Good knowledge on scripting (Python, Perl and Shell scripting) Knowledge of power, performance, and area (PPA) optimization techniques. Experience with designing for low-power, high-speed circuits is highly desirable. Excellent communication skills and the ability to work in a team environment.

FPGA Developer --> --> Location, Designation --> LocationRemote DesignationFPGA Developer Experience7- 9 Years Skills required: 1. Should have worked on USRP N310/X310 (N3xx/X3x0) 2. In-depth Knowledge of FPGA Architecture 3. Able to write own RTL custom HDL or drops in IP a) VHDL, Verilog, System,Verilog, Vivado HLS b) Xilinx IP, Vivado Block Diagram 4. Should have developed RFNoC Block 5. Have working knowledge of USRP Hardware Driver (UHD) 6. Able to write custom FPGA logic in RFNoC Blocks 7. Able to use library of existing RFNoC Blocks a) FFT, FIR, Signal Generator, Fosphor 8. Have understanding of GNU Radio interface to RFNoC Block 9. FPGA debugging and HW/SW integration 10. Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed 11. In-depth knowledge of XILINX ZYNQ 71xx/pl-kINTEX-7 based RFNoC architecture is must. 12.Understand Customer requirements, define architecture and detailed design 13. Good Customer Communication Skills 14. Working knowledge of Agile Feel Free To Contact Us...!!! Submit

CATIA V6 Working Experience on Using CATIA V6 & PLM application. Experience in Wheels ,Tyres & Braking System Stellantis know-how Synthesis and verification of the necessary input data/documents. Develop supplier consultation files (Int/Ext) for a 'complex' component in series production or a 'simple/complex' component purchased as part of a new PTF or new vehicle, or a 'simple/complex' component in development Manage the BE Formalization of consultation documents for a 'complex' component in series production or a 'simple/complex' component purchased as part of a new PTF or new vehicle, or a 'simple/complex' component in development Supplier management (including new) Technical reviews Management of the Development Schedule Management of the Organic and Subsystem Digital and Physical Validation Plan Management of quality/Risk convergence Project Reporting Use of CAD software or other specific software Contribute the QCDP synthesis of the component/Capitalization

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers. Skills (competencies)

Required Skills Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills

Responsibilities Understand the standards/specifications Architecture development and documenting implementation level details Hands on work for every aspect of verification cycle Responsible for the compliance with the latest Methodologies. Developing Verification IPs Define Functional Coverage matrix and Comprehensive Test plan Regression management and functional coverage closure DUT integration and verification for IP delivery sign-off Leading small team Person Specification Required Skills Hands-on experience of complete verification cycle with strong verification concepts Strong knowledge of Verilog, SystemVerilog and UVM Experience in UVM based Verification IP development Experience in AMBA AXI/AHB/APB System buses Hands on work experience on any of PCIe/Eth/USB/DDR etc. Hands on experience with System Verilog Assertions Scripting for automation, release process, simulations, regressions Good command over written and oral communication Desirable Skills Lead the Verification IP development with 2 or more junior engineers Exposure to full verification cycle Desired Skills and Experience DV Engineer, Design Verification, Verification Engineer

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com call me :7995220108. Client Name: Proxelera Industry: SEMICON Position Name RTL Design Lead/uArch/Design Engineer Position type: Permanent Total Exp: 10-15 years HBTS Budget: Open Notice Period: Immediate to 15days Work Location: Bangalore Job Description Must have: We're looking for a highly skilled RTL Design Lead to lead our digital design team. The successful candidate will be responsible for designing, developing, and verifying complex digital circuits using RTL design methodologies. The RTL Design Lead will work closely with cross-functional teams to ensure seamless integration of digital design blocks into larger systems. Key Responsibilities: 1. Lead a team of RTL designers to design, develop, and verify complex digital circuits. 2. Develop and maintain RTL design methodologies, standards, and best practices. 3. Collaborate with architects to define and implement digital architecture. 4. Work closely with verification teams to ensure seamless integration of digital design blocks. 5. Participate in design reviews, provide feedback, and ensure design quality. 6. Develop and manage project schedules, resource allocation, and budgets. 7. Mentor and train junior designers to improve team capabilities. Requirements: 1. Bachelor's/Master's degree in Electrical Engineering, Computer Science, or related field. 2. 10+ years of experience in RTL design, with at least 3 years in a RTL design/uArch leadership role. 3. Strong expertise in digital design principles, RTL design methodologies, and verification techniques. 4. Proficiency in HDLs (Verilog/SystemVerilog/VHDL), design tools (e.g., Synopsys, Cadence), and scripting languages (e.g., Perl, Python). 5. Excellent leadership, communication, and project management skills. 6. Strong problem-solving skills, with the ability to analyze complex design issues. Nice to Have: 1. Experience with ASIC/FPGA design flows. 2. Knowledge of computer architecture, microprocessors, and embedded systems. 3. Familiarity with industry-standard design methodologies (e.g., OVM, UVM). 4. Certification in RTL design or related field. AMD (Dont Share AMD Profiles) Preferred candidate profile

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL Engineer Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: Key Responsibilities: Understand RTL at structural level, IP boundaries, IP parameters. Understand IP design. Add assertions where needed. Generate various constraints necessary for the IP. RTL build flow setup and maintenance. Do the quality checks of the IP like Lint/CDC/RDC/Synth/Timing checks/waiver creation across milestones. Participate in IP integration to the subsystem level. Write sample test bench to verify the basic functionality of the IP/block. Do the first level of triage of the functional issues reported. Understand the reports out of quality checks such as Lint/CDC/RDC/Synth/Timing checks and suggest fix in the RTL Work with functional verification team to meet coverage and quality standards. Guarantee quality/timely deliverables meeting projects schedule. Help to improve/automate design process. PREFERRED EXPERIENCE: Knowledge of ASIC development flows Knowledge of front-end RTL design tools and methodologies. Knowledge of system Verilog Multi-clock domain designs. Design constraints for synthesis and static timing analysis. Experience in RTL linting tools, reset domain crossings, clock domain crossings, synthesis, RAM generation (area, timing, power) Knowledge of AXI/AMBA protocol Ability to create a simple SV based Test benches, create sanity test plan, run the test cases Knowledge of front-end requirements and deliverables for verification, validation, physical design, architecture, security, dfx, power. Verification - coverage, test plan, debug Physical design – timing, clock crossings, reset crossings, ECOs (manual, formal) Ability to work and effectively collaborate with partners Knowledge of scripting languages like Perl, tcl or cshell Experience with DMAs, PCIe, ordering, data path virtualization, performance, flow control a plus. TekWissen® Group is an equal opportunity employer supporting workforce diversity.

1+ Yrs Experience working on modern front-end web technologies, including: React, JS(ES6+) TypeScript, Next.js, HTML5, CSS3 and Less/Sass ability to write mixins, partials, functions, etc developing highly-optimized applications using React and Redux Required Candidate profile Experience interning in the E-Commerce Experience with the standard tooling Webpack, Babel, Linting, JS Typing, and Prettier. Experience in Caching

Experienced in rtl design using verilog / system Verilog Asic designers with experiences in all aspects of rtl design flow from specification/microarchitecture definition to design and verification, timing analysis, dft and implementation Integration, rtl signoff tools, upf/low power signoff and cdc/rdc, lint Strong domain knowledge of clocking, system modes. Power management, debug, interconnect, safety, security and other architectures

3+Yrs Exp.Android device platform, Proficient In Kotlin Language knowledge of design patterns like MVP, MMVM, RxJava, and others knowledge of Android SDK, NDK, Android Studio, Gradle, and Lint Knowledge of Flutter or React native will be an advantage Required Candidate profile Candidate will be able to build and integrate android libraries and modules and design-build and maintain high performance reusable java and OOPS concept

Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based onImplementation means trying, testing, and improving outcomes until a final solution emerges . Knowledge means exchange discussions with colleagues from all over the world. Join our team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation. We make real what matters. This is your role. Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will get along with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We dont need superheroes, just super minds. You're an Electronics Engineer ( B.Tech / M.Tech ) or related field from a reputed institute You've got phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well. You've sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe , Flash, DIMM etc. You are a great teammate, resilient and sincere, Enjoy learning new things and build knowledge base in new area. Weve got quite a lot to offer. How about you This role is based in" Noida " but " youll get the chance to work with teams impacting entire cities, countries- and the shape of things to come. The pace of innovation in electronics is constantly accelerating. To enable our customers to deliver life-changing innovations to the world faster and to become market leaders, we are committed to delivering the worlds most comprehensive portfolio of electronic design automation (EDA) software, hardware, and services. We, at Siemens EDA enable companies to develop better electronic products faster and more efficiently. Our innovative products and solutions help engineers conquer design challenges in the increasingly sophisticated worlds of board and chip design We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. About the role: We are seeking a highly motivated and detail-oriented Application Support Engineer to join our dynamic, fast paced and growth-mindset team. In this role, you will be focused on supporting the Questa verification products, specifically in Verification IP line of products. In this position, you will be working closely with the product engineering team, field application engineers and customers. As an ASE, you will be solving some of our customers complex design, testbench and environment issues in the domain of functional verification. You will also be working closely on creating knowledge-based content and providing expertise on the Questa platform. You will work with multiple customers to understand their challenges and flow and be involved in technical presentations, training, evaluation and competitive benchmarking. You will part of the larger application support engineering organization and will be interfacing regularly with the North American and PACRIM teams. Minimum Qualifications BS Electronic/Computer Engineering from an accredited institution Minimum of 2+ years of Digital Design/Verification experience Knowledge of VHDL or Verilog, or SystemVerilog RTL languages for ASIC or FPGA design Experience with ASIC or FPGA hardware design and implementation using RTL tool flows and methodologies Knowledge of Windows and Linux OS Self-motivated, flexible, self-disciplined, and comfortable in a dynamic, quick-moving environment. Strong interpersonal and communications skills with the ability to quickly establish rapport and credibility with our customers, sales, and product teams. Strong oral, and written communication, and presentation skills Excellent organizational and time management skills Preferred qualifications MS Electronic/Computer Engineering Knowledge of UVM and System Verilog for Verification Clock Domain Crossing (CDC), Static and Formal Verification- Formal Applications Working knowledge of Working knowledge of Questa-Modelsim, VCS (Synopsys), NCSim (Cadence) or Aldec simulators. Knowledge of C/C++ programming languages Demonstrated proficiency with Object-Oriented Programming experience in test bench architecture and design Knowledge of scripting languages (e.g., Shell, Tcl, Perl, Python) Knowledge of CDC, low power and formal methodologies. Location Noida/ Bangalore Why us Working at Siemens Software means flexibility - Choosing between working at home and the office at other times is the norm here. We offer great benefits and rewards, as you'd expect from a world leader in industrial software. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! Siemens Software. Transform the Everyday #Li-EDA #LI-HYBRID

* Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering.* Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment.* Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU.* Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments.* Develop verification test plan for both functional and performance verification including the estimation for coverage closure.* Support higher level core/system simulation environment.* Participate in post silicon lab bring-up and validation of the Hardware.* Lead , guide ,mentor a team of engineers and represent them at global forums.* Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement.* Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. * Hands-on on Power Management domain Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 4 years or more experience in functional verification of processors, demonstrating a deep understanding of power management unit verification.* Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. * Experience with high frequency, instruction pipeline designs* At least 1 generation of Processor Core silicon bring up experience* In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs)* Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design* Proficiency in C++, Python scripting or similar object oriented programming languages.2:37Y Annapurna Bharathi Preferred technical and professional experience * Knowledge of instruction dispatch and Arithmetic units.* Knowledge of test generation tools and working with ISA reference model.* Experience with translating ISA specifications to testplan.* Knowledge of verification principles and coverage.* Understanding of Agile development processes. * Experience with DevOps design methodologies and tools.

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -12+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Responsibilities: Should have good understanding of SoC design flow Hands-on expertise in writing RTL in Verilog and System Verilog (optional VHDL) language, SoC level RTL integration ,Linting, CDC checks, STA ,constraints, UPF

RTL Design Engineer (5+years experience) Company: HCL Tech Job Summary: We are looking for a talented and experienced RTL Design Engineer to join our team and play a key role in the design and development of next-generation ASICs/SoCs. You will be responsible for all aspects of RTL design, from concept to RTL coding, verification, and integration. Responsibilities: Develop RTL code for complex digital circuits using Hardware Description Languages (HDLs) such as Verilog or VHDL Perform functional verification using simulation and formal methods Participate in code reviews and ensure adherence to coding standards Analyze timing performance and perform static timing analysis (STA) Collaborate with design, verification, and synthesis teams to ensure successful tape-out Stay up-to-date with the latest RTL design methodologies and tools Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5+years of experience in RTL design for ASICs/SoCs Proven experience in designing and verifying complex digital circuits Proficiency in Verilog or VHDL Experience with verification methodologies (e.g., UVM) Strong understanding of digital design concepts (combinational logic, sequential logic, state machines) Experience with SDC (Standard Delay Constraint) format for timing closure Experience with scripting languages (e.g., Python, Perl) is a plus Excellent communication, teamwork, and problem-solving skills Benefits: Competitive salary and benefits package Opportunity to work on cutting-edge technologies Collaborative and fast-paced work environment Potential for professional growth and development.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL Lead Engineer Location: Mysore Work Type: Onsite Job Type: Full time Job Description: Strong proficiency in Verilog and SystemVerilog, with experience in designing finite state machines (FSMs), clocking, reset strategies, and bus architectures. Capable of developing microarchitecture from specification to RTL, including block and subsystem design, as well as thorough documentation. Skilled in RTL debugging, with working knowledge of synthesis processes and timing closure. Familiar with industry protocols and integration, such as AXI, APB, AHB, PCIe, SoC integration, design-for-test (DFT), and power domain management. Good to Have Skills: Experience with scripting and automation using Python, Tcl, or Perl to streamline design flows. Demonstrated leadership and collaboration abilities, including mentoring, cross-functional communication, AMS integration, UPF-based low-power design, post-silicon debugging, and a proactive approach to automation TekWissen Group is an equal opportunity employer supporting workforce diversity.