477 Rtl Coding Jobs - Page 2

Job Description We are looking for an experienced Design Verification Engineer to join our team and contribute to the verification of complex SoC/ASIC designs. The ideal candidate will have strong expertise in verification methodologies, testbench development, and debugging. Key Responsibilities: Develop and implement verification plans, environments, and testbenches using SystemVerilog/UVM. Write and execute test cases for functional, regression, and coverage-driven verification. Perform debugging and root cause analysis for design and verification issues. Collaborate with RTL design, architecture, and validation teams to ensure quality deliverables. Analyze functional coverage metrics and enhance test suites for improved quality. Work on assertion-based and formal verification techniques where applicable. Contribute to automation and scripting to streamline verification flows.

Education: Bachelors degree (BE/B.Tech)orMasters degree (ME/M.Tech) Roles & Responsibilities: Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team. Write and perform the test plan in close cooperation with the logical design team. Develop coverage models and verification environments using UVM-SystemVerilog C++. Write, maintain and publish the verification specification. Monitor, analyze and debug simulation errors. Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time. Produce a maintainable and reusable code across projects Required Skills and Experience Curious, demanding and rigorous. Mastering object oriented programming. Knowledge of UVM verification methodology (or equivalent) and SystemVerilog SystemC hardware verification languages Knowledge of Constraint-Random Coverage-Driven verification environments development in SystemVerilog C ++ (drivers monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp SVA) Knowledge of simulation tools and coverage database visualization tools Effective in problems solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints. Our Offering: Competitive salary package Leave Policies: 10 Days of Public Holiday (Includes 2 days optional) & 22 days of Earned Leave (EL) & 11 days for sick or caregiving leave. Benefit Plans (Insurance) Medical & Life & Accidental & EDLI

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) Mandatory Skills: RTL coding.Experience: 5-8 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: RTL coding.Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: Semiconductor Integration. Experience: 3-5 Years.

The people are the culture. We encourage a culture of passion for technology solutions that impact businesses. We also make sure that our people pursue their individual passions. Working with us means you get an in-depth understanding of a range of industries and emerging technologies that help us build solutions that are futuristic and impactful. More importantly, the experience of being at MarvyLogic may help you evolve as a person toward enjoying a more fulfilling life. Minimum BE/BS degree in Electrical/Electronics/Computer science required. At least 5-10 years of logic design and RTL coding experience with sound knowledge on verification and implementation concepts. Experience in physical layer ASIC architecture, micro-architecture development, design and debug. Ability to code readable, maintainable, verifiable and synthesizable logic in Verilog and/or SystemVerilog. Experience with lint, synthesis, CDC, STA, formality, ECO process, tool flows, and scripting. Knowledge in one or more of the following areas, a definite plus: Ethernet (layer 2/3/4 protocols, GMII/XGMII, integration of PHY layer), DSP fundamentals/Filter/FFT design/Datapath design/Error Control Coding, Computer architecture/Processor fundamentals. Preferred Qualifications: Strong knowledge of ASIC design methodologies and flows. Ability to proactively take on responsibilities and competent to work in a start-up environment. Worked with product development companies and having seen at least a couple of tape-outs. Experience with silicon bring-up in the lab and debugging is a definite plus. Experience with FPGA realizations of higher complexity designs. Ability to work with teams spread across geography with excellent communication skills. Responsibilities: Develop key blocks of logic in a next-generation physical layer/mixed signal SOCs. Perform hardware feasibility analysis and come up with a micro-architecture specification helping it map to a high performance, implementable design. Work with verification, DFT, synthesis, circuits, backend implementation teams to realize quality implementation.,

You have an immediate job opening with one of your valuable clients in Hyderabad for FPGA with Firmware profiles. The ideal candidate should have at least 8 years of experience in FPGA, RTL Design, RTL Coding, Firmware, CDC, and Lint. The location for this position is Hyderabad and the notice period is immediate to 15 days. If you are interested in this opportunity, kindly share your updated profile with Anand Arumugam at anand.arumugam@modernchipsolutions.com or call +919900927620 for further discussion.,

The role involves designing and architecting VLSI and hardware-based products to facilitate exceptional client engagement and satisfaction. Key responsibilities include defining product requirements, implementing VLSI and hardware devices, upgrading design tools, analyzing hardware components, conducting cost-benefit analysis, and developing architectural designs. Additionally, the role requires understanding market-driven business needs, defining architecture requirements and strategies, creating proof of concepts, and providing technical leadership in product development. Moreover, the role involves collaborating with various teams, analyzing technology environments and client requirements, providing technical solutions to RFPs, validating prototypes, identifying problem areas, and maintaining product roadmaps. Competency building and branding activities such as completing necessary trainings, developing proof of concepts, writing white papers, and mentoring junior architects are also part of the role. The candidate must have mandatory skills in RTL coding and possess 8-10 years of experience in the field. The job offers an opportunity to be part of a dynamic team at Wipro, a company that encourages reinvention, evolution, and empowerment. Applications from individuals with disabilities are encouraged. Performance Parameters: 1. Product design, engineering, and implementation: Measured by CSAT, quality of design/architecture, FTR, delivery adherence to cost, quality, and timeline, POC review, and standards. 2. Capability development: Percentage of trainings and certifications completed, mentoring of technical teams, development of thought leadership content (white papers, Wipro PoVs).,

You should have a Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, focusing on computer architecture, or equivalent practical experience. With 4 years of experience in RTL coding and experience with RTL quality checks methodologies such as Lint, CDC, RDC. A Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with a specialization in computer architecture is preferred. Experience in implementing Camera ISP image processing blocks, Video processing blocks, Machine Learning IPs, or other multimedia IPs like Display or Video Codecs would be advantageous. Also, familiarity with ASIC design methodologies for clock domain checks and reset checks is preferred. Join a team that pioneers innovation, crafting custom silicon solutions to drive the future of Google's direct-to-consumer products. Contribute to developing products that are adored by millions worldwide, shaping the next generation of hardware experiences for unparalleled performance, efficiency, and integration. The gChips team focuses on custom silicon solutions that enhance user experiences in Google Hardware products, optimizing performance and power for specific use cases. This includes SoCs and other integrated circuits for the product portfolio. Collaborating with various teams across Google, gChips identifies silicon requirements for the future and stays informed about the latest chip technologies and standards. As part of the team designing interconnect IP for Pixel SoCs, you will work with architecture, software, verification, power, timing, and synthesis teams to deliver quality RTL. Your responsibilities will include developing microarchitecture, Verilog/SystemVerilog RTL coding, simulation debugging, and RTL implementations meeting power, performance, and area goals. You will also be involved in synthesis, timing/power closure, pre-silicon, and post-silicon bring-up, along with collaborating with global teams at different sites. Google's mission is to make the world's information universally accessible and useful, combining AI, Software, and Hardware expertise to create innovative experiences. By researching, designing, and developing new technologies, we aim to enhance computing speed, seamlessness, and power, ultimately improving people's lives through technology. Your responsibilities will involve collaborating with architects to develop microarchitecture, RTL coding, and performing simulation, debug, and quality checks. You will work on RTL implementations meeting power, performance, and area goals, participate in synthesis and timing/power closure, and support pre-silicon and post-silicon activities. Additionally, you will travel to collaborate with global teams at different sites worldwide.,

You will be responsible for Logic design, micro-architecture, and RTL coding, with hands-on experience in SoC design and integration for complex SoCs. It is essential to have expertise in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, as well as SoC clocking, reset, debug architecture, and peripherals such as USB, PCIE, and SDCC. Understanding Memory controller designs and microprocessors will be advantageous. Collaborating closely with SoC verification and validation teams for pre/post Silicon debug is a key aspect of this role. Your role will require hands-on experience in Low power SoC design, Multi Clock designs, and Asynchronous interfaces. Proficiency in using ASIC development tools such as Lint, CDC, Design compiler, and Primetime is necessary. An understanding of constraint development and timing closure will be a plus. Experience in Synthesis and knowledge of timing concepts will also be beneficial. Additionally, experience in creating padring and collaborating with the chip-level floorplan team is desirable. You must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 6 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 5+ years of relevant experience or a PhD with 4+ years of relevant experience will also be considered. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. Reasonable accommodations will be provided upon request to support individuals with disabilities in the hiring process. The company expects all employees to adhere to relevant policies and procedures, including security protocols and confidentiality requirements. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies. Staffing and recruiting agencies, as well as individuals being represented by an agency, are not authorized to submit profiles, applications, or resumes through the Qualcomm Careers Site. For more information about this role, please reach out to Qualcomm Careers.,

This role is for an IP / SoC RTL Senior / Lead Design Engineer to be responsible for the development and integration of IP and sub-systems. The ideal candidate will have strong expertise in logic design, RTL coding, and ASIC development, with a focus on creating high-performance, complex digital designs. Responsibilities Responsible for IP / sub-system level micro-architecture development and RTL coding . Prepare block/sub-system level timing constraints . Integrate IP/sub-system into larger designs. Perform basic verification in either an IP verification environment or on an FPGA. Skills Expertise in Verilog is a must. Experience in Logic design, micro-architecture, and RTL coding is essential. Knowledge of AMBA protocols - AXI, AHB, APB . Experience in synthesis and a strong understanding of timing concepts for ASIC development. Hands-on experience in multi-clock designs and asynchronous interfaces is a must. Experience with tools used in all phases of ASIC development, such as Lint, CDC, and Simulation . Knowledge of low power concepts is a plus. Experience in designing controllers for complex protocols like DDR, USB, or PCIe is a plus. Qualifications B.Tech. or M.Tech. with relevant experience. Immediate availability is preferred

Job description Asic Design Engineering Manager Responsibilities Manage an ASIC design team responsible for various processing blocks in a SOC. Drive RTL design planning and execution, innovative design methodology development, u-Arch, IP design and SOC integration. Participate in silicon architecture, interface with Architecture, SW/FW, Design, Modelling, Emulation, and Post-Silicon Validation teams Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, capacity planners and supply chain experts Contribute to and drive development of and maintain overall silicon strategy aligned to corporations Long Range Plan objectives Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection and IP licensing Build, lead, and support a team of ASIC engineers through strategic hiring, training, and guidance to drive on-time and on-budget product delivery Contribute to, analyze, review SOWs from vendors, supporting documentation, requirements sets that meet the needs of internal customers Support engineering teams to define, debug, implement and deliver total solutions around purpose built ASICs Define, implement and maintain key performance indicators (KPI) for areas of responsibility Partner with technical program management and supply chain team members to manage external development partners, suppliers and vendors Minimum Qualifications B.S. or M.S. degree in Computer Engineering or Electrical Engineering, relevant technical field, or equivalent practical experience 12+ years experience in ASIC/SoC RTL design 3+ years of experience as a People Manager Clear understanding of complexities involved with various RTL design tools, including Synopsys DC compiler, Cadence LEC, Spyglass. Track record of first-pass success in ASIC Development Experience working across multiple projects and adjusting priorities in partnership with stakeholders Experience with interpreting functional specs and creating comprehensive u-Arch Preferred Qualifications Hands-on experience with complex subsystems like memory/LPDDR/HBM, cache, PCIE or Network on chip. In depth knowledge of at least one of these areas - NICs, signal processing algorithms, neural networks and machine learning concepts, and/or other neural network development framework

Job description Meta is looking for Asic Engineer, EDA Infrastructure to join our dynamic team and embark on a rewarding career journey. Your role involves working on complex projects and ensuring that ASICs meet performance, power, and area requirements. Key Responsibilities : Design Planning : Collaborate with cross-functional teams to define project goals, scope, and design requirements for ASIC projects. Establish design plans, including specifications, milestones, and budgets. Architecture and Microarchitecture : Create architectural and microarchitectural specifications for ASIC designs, outlining high-level structure and functionality. RTL Design : Implement ASIC designs using hardware description languages (HDL) such as Verilog or VHDL. Develop and optimize RTL (Register Transfer Level) code for logic design. Synthesis and Optimization : Perform synthesis and optimization to ensure the ASIC design meets performance, power, and area targets. Work on clock domain crossing, power management, and timing closure. Verification Support : Collaborate with ASIC Verification Engineers to develop and implement testbenches and test scenarios to validate ASIC functionality. Debug and resolve design issues identified during verification. DFT (Design for Test) : Implement DFT features, such as scan chains and boundary scan, to facilitate efficient testing of the ASIC. Low-Power Design : Optimize ASIC designs for low-power operation, including clock gating, voltage scaling, and power gating. Physical Design Support : Work with physical design and layout teams to ensure proper floor planning and placement of ASIC components. Documentation : Maintain comprehensive and well-organized documentation of design specifications, RTL code, and design decisions. Technology and Tool Awareness : Stay updated on semiconductor technologies, ASIC design tools, and industry best practices to enhance design processes. Collaboration : Collaborate closely with cross-functional teams, including verification, software, and project management, to achieve project goals.

Job description ASIC Engineer Design Responsibilities Architecture exploration Micro-architecture development RTL development using Verilog, System Verilog and HLS Lint, CDC, Synthesis, Power Optimization Soft and hard IP identification, selection and integration Collaboration with verification and emulation teams in test plan development and debug Collaboration with implementation team to close the design on timing and power Minimum Qualifications At least 7+ years of silicon development experience Track record of first-pass success in ASIC Development Experience with Verilog or System Verilog Experience in one of these skills: Micro-architecture and RTL development for complex control and data path IPs, OR Experience in SoC Micro-architecture, Design and Integration, OR Implementation, Power methodology development Experience working across multiple projects Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Preferred Qualifications Experience in data path development Experience in CPU, NOC, Memory and Peripheral Subsystems Experience in HLS Experience with Synthesis, Timing Closure and Formal Verification Methodology Experience with Power Analysis and Optimization Experience with scripting languages (TCL, Python, Perl, Shell-scripting)

Job description Meta is looking for ASIC Engineer, Host & Userspace, Infra Silicon Enablement to join our dynamic team and embark on a rewarding career journey. Develop and implement ASIC design methodologies, including design, verification, and testing Collaborate with cross-functional teams to identify and understand requirements and develop solutions that meet business needs Develop and maintain design specifications, test plans, and documentation Participate in the full ASIC development cycle, including architecture, RTL design, verification, and synthesis Perform design optimization and analysis to ensure optimal performance and power efficiency Ensure compliance with industry standards and guidelines. Strong knowledge of ASIC design methodologies and tools. Excellent communication and interpersonal skills Strong analytical and problem-solving skills

Job description Meta is looking for ASIC Engineer, Power to join our dynamic team and embark on a rewarding career journey. Develop and implement ASIC design methodologies, including design, verification, and testing Collaborate with cross-functional teams to identify and understand requirements and develop solutions that meet business needs Develop and maintain design specifications, test plans, and documentation Participate in the full ASIC development cycle, including architecture, RTL design, verification, and synthesis Perform design optimization and analysis to ensure optimal performance and power efficiency Ensure compliance with industry standards and guidelines. Strong knowledge of ASIC design methodologies and tools. Excellent communication and interpersonal skills Strong analytical and problem-solving skills

Job description Meta is looking for ASIC Engineer - Infra Specialist to join our dynamic team and embark on a rewarding career journey. Develop and implement ASIC design methodologies, including design, verification, and testing Collaborate with cross-functional teams to identify and understand requirements and develop solutions that meet business needs Develop and maintain design specifications, test plans, and documentation Participate in the full ASIC development cycle, including architecture, RTL design, verification, and synthesis Perform design optimization and analysis to ensure optimal performance and power efficiency Ensure compliance with industry standards and guidelines. Strong knowledge of ASIC design methodologies and tools. Excellent communication and interpersonal skills Strong analytical and problem-solving skills

Qualcomm India Private Limited is seeking a candidate with a minimum of 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FV. The ideal candidate should have experience in Logic design/micro-architecture/RTL coding, along with hands-on experience in designing and integrating complex multi clock domain blocks. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, clocking/reset/debug architecture are necessary. Experience in Multi Clock designs and Asynchronous interface is a must, as well as familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime. Collaboration with Design verification and validation teams for pre/post Silicon debug is expected, and hands-on experience in Low power design is preferable. Additionally, experience in Synthesis and understanding of timing concepts for ASIC is essential. The minimum qualifications for this position include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in the relevant fields with 2+ years of experience or a PhD with 1+ year of experience would also be considered. Qualcomm is an equal opportunity employer committed to providing accessibility to individuals with disabilities throughout the application/hiring process. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. Employees are expected to adhere to all applicable policies and procedures, including security and confidentiality requirements. Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use the site or submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not bear responsibility for any fees related to such submissions. For more information about this role, please contact Qualcomm Careers.,

Key Responsibilities 01 years of hands-on experience in implementing designs on FPGA Strong expertise in RTL coding using VHDL/Verilog/System Verilog Understanding of FPGA design flow including constraint definition, synthesis, floor planning, place & route, and timing closure Create block-level design documentation Write testbenches and sequences in SystemVerilog Work with lab equipment for validation and testing Familiarity with standard interface protocols (e.g., SPI, I2C, UART, etc.) Knowledge of modern FPGA architectures Exposure to scripting languages for automation Preferred Experience Hands-on experience with FPGA design tools like Libero Experience with Tcl/Perl/Python scripting Good debugging skills (both hardware and software) Understanding of Clock Domain Crossing (CDC) checks Knowledge of synthesis and static timing analysis Familiarity with FPGA hardware design is an added advantage Benefits Real-world exposure to cutting-edge space technology projects Mentorship from experienced FPGA and space systems engineers Collaborative, growth-oriented team environment Fun, engaging, and fast-paced work culture

Job Description Change the world. Love your job. In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system. Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level. As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments. This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork. Qualifications Minimum requirements: 8 years of relevant experience A thorough understanding of digital logic design Familiarity with the Verilog language and simulators A good understanding of analog functionality and exposure to analog IC design methods Ability to solve problems using a systematic approach Preferred Qualifications Experience with System Verilog Demonstrated strong analytical and problem solving skills Strong verbal and written communication skills Ability to work in teams and collaborate effectively with people in different functions Strong time management skills that enable on-time project delivery Demonstrated ability to build strong, influential relationships Ability to work effectively in a fast-paced and rapidly changing environment Ability to take the initiative and drive for results About Us Why TI Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We&aposre different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com . Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. About The Team TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment. Show more Show less

You have an immediate job opening with one of our valuable clients in HYD locations for FPGA with Firmware profiles. The ideal candidate should have a minimum of 8 years of experience in FPGA, RTL Design, RTL Coding, Firmware, CDC, and Lint. The location for this position is in HYD with a notice period of immediate to 15 days. If you are interested in this opportunity, kindly share your updated profile with Anand Arumugam at anand.arumugam@modernchipsolutions.com or call at +919900927620 for further discussion.,

The DCAI and Silicon Eng Team is responsible for delivering leadership Xeon products to cloud and datacenter customers by developing industry-leading x86 core and differentiated IPs. These IPs enhance product performance and competitiveness in both Xeon and AI platforms. The IP design group within DCAI focuses on designing Coherent Fabric IP, Memory controller, NOC, PCIE, and other fundamental building blocks for Xeon server SOCs. We are currently looking for an experienced Senior Micro Architect to design, develop, and implement advanced Digital IO Controllers such as PCIe/CXL/UCIe systems for next-generation data center and AI chips. This role requires a unique blend of architectural expertise and hands-on RTL coding skills to bring cutting-edge designs to life. The ideal candidate will possess a deep understanding of high-speed IOs like PCIe/CXL/UCIe architecture, interconnect protocols, and coherence mechanisms, along with a proven ability to implement these designs at the RTL level. Key Responsibilities: - Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs. - Design and implement critical components of the memory fabric microarchitecture, including coherency controllers and interconnect blocks. - Develop RTL code for core components of the memory fabric, ensuring optimal performance, area, and power trade-offs. - Collaborate closely with verification teams to create test plans and debug issues during pre-silicon validation. - Work with cross-functional teams (physical design, software, and firmware) to ensure seamless integration of memory fabric systems. - Analyze system performance, conduct workload modeling, and optimize the architecture for target use cases. - Mentor junior engineers, contribute to technical reviews, and design documentation. - Stay updated with emerging technologies and trends in PCIe/CXL/UCIe protocols, as well as AI/ML hardware. - Demonstrate strong problem-solving and debugging skills. - Exhibit excellent communication and collaboration abilities. - Ability to manage and prioritize multiple tasks effectively. Qualifications: - Bachelor's degree with 15+ years of experience or Master's degree in Electronics and Computer Engineering with relevant experience of at least 10+ years. This is an Experienced Hire job type located in India, Bangalore, within the Design Engineering Group (DEG) at Intel. DEG is committed to developing best-in-class SOCs, Cores, and IPs that power Intel's products. The team focuses on delivering leadership products through the pursuit of Moore's Law and groundbreaking innovations. This role is eligible for a hybrid work model allowing employees to split their time between working on-site at the assigned Intel site and off-site. Please note that job posting details, such as work model, location, or time type, are subject to change.,

You will be responsible for demonstrating expertise in RTL Coding using Verilog, System Verilog, or VHDL. Your role will involve a strong understanding of FPGA flow, Logic design, and Digital design. It is essential to have knowledge in FPGA architecture and proficiency in Tcl and Python scripting. You will be conducting Vivado testing of synthesis tool and other stages. This position does not entail Silicon RTL development or any HW flow or testing. Your communication skills are crucial, as you will be expected to communicate technical information in an organized and understandable manner. A customer-oriented approach is necessary, along with a demonstrated concern and willingness to assist customers. Good organizational skills, multitasking abilities, prioritization, and activity tracking are essential. Exceptional oral and written communication skills are also required. TekWissen Group is committed to equal employment opportunities and supports workforce diversity.,

ViewRay Systems is looking for a Senior FPGA Design Engineer to join our team in Chandigarh, India. As a Senior FPGA Design Engineer at ViewRay Systems, you will be instrumental in our mission to innovate and develop cutting-edge cancer therapy systems. You will play a crucial role in developing electrical system solutions from the conceptual stage to production, ensuring high-quality requirements for components and modules, and collaborating with the team to achieve project goals and architecture. Your responsibilities will include developing FPGA modules that cover a range of functionalities such as sensor interfaces, data acquisition systems, communication modules, signal processing, adaptive controls, memory management, and software-hardware interfaces. You will work closely with fellow engineers to expand FPGA design and integrate hardware effectively. Additionally, you will be responsible for leading electrical-software integration efforts, performing data analysis, and developing test methods to ensure the safe and effective operation of new products. To be successful in this role, you should hold a BSEE or related degree with at least 6 years of experience and demonstrate a strong understanding of FPGA development platforms like AMD/Xilinx Vivado, VHDL, RTL coding practices, and basic circuit design principles. Excellent communication skills, both verbal and written, are essential to effectively convey ideas and collaborate with team members. Experience with standards such as IEC 60601, proficiency in Python for analyzing and testing FPGA modules, and technical leadership skills are highly preferred. This is a full-time position that requires in-person work at our office in Chandigarh, India. Relocation to the area before starting work is mandatory. We offer health insurance, Provident Fund benefits, and day shift schedules. If you have a minimum of 3 years of experience as an FPGA Design Engineer and are ready to contribute to groundbreaking cancer therapy innovations, we encourage you to apply for this exciting opportunity at ViewRay Systems India Private Limited. #Job Type: Full-time #Work Location: In person in Chandigarh, India: Relocate before starting work VIEWRAY SYSTEMS INDIA PRIVATE LIMITED PLOT NO. A-40A, INDUSTRIAL FOCAL POINT, PHASE 8-EXTN, Sector 59, S.A.S.Nagar (Mohali), Distt. Mohali, Punjab -160059,

Are you looking for a unique opportunity to be a part of something great Want to join a 20,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchips nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and its won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Create System and FPGA designs to exercise all the use models targeted for each product mimicking end applications in a customer setting. Write system and product level validation plans for new and existing silicon products and projects; execute per plan, record and communicate results. FPGA prototyping and emulation. Understanding spec., writing emulation plan and executing per plan. Record and communicate results. Understand hardware architectures, use models and system level design implementations required to utilize the silicon features. Be an effective contributor in a cross-functional team-oriented environment. Write high-quality code in Verilog, VHDL, and C code for embedded processors. Maintain existing code. Learn new system designs and validation methodologies. Understand FPGA architectures. Be conversant with on-chip debug tool. Requirements/Qualifications: - Excellent verbal and written communication skills in English - 5+ Years experience in Design with RTL coding in Verilog and VHDL and Verification of RTL - Possess an in-depth understanding of hardware architectures, system-level IC design implementation, knowledge of how to create end-use scenarios - Optimizing code for FPGA architectures - Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools - Basic knowledge of embedded processors such as ARM Cortex-M3 or RISC and familiarity with AMBA protocols APB, AHB, AXI, ACE - Working knowledge of embedded software C/C++ is also a plus - Strong technical background in FPGA prototype emulation, and debug - Strong technical background in silicon validation, failure analysis, and debug - Excellent Board level debug capabilities in a lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCBs using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Idenitfy, Xilinx Chipscope, Altera Signalscope, Lattice Reveal - Design with RTL coding in Verilog and VHDL is a must - Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools - Hands-on systems level design and debug experience with at least two of the following high-speed serial communications protocols: PCIe Gen1/2/3, Interlaken (10.3125 Gbps), CPRI (614.4Mbps - 12.672 Gbps), SGMII or QSGMII, XAUI or HiGig/+/II, 10GBASE-R/-KR, Serial Rapid IO Travel Time: 0% - 25% To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.,