477 Rtl Coding Jobs - Page 4

Were hiring a talented RTL Design Engineer to join our team in Hyderabad and contribute to advanced ASIC/SoC projects. Key Responsibilities: Perform RTL integration for ASIC/SoC designs Debug CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) violations Analyze and resolve timing and CLP (Clock Level Planning) issues Apply strong digital design fundamentals in RTL development Tackle complex design problems with excellent debugging skills Requirements: 3+ years of experience in RTL design and integration Solid foundation in digital logic design Strong problem-solving and debugging abilities

Candidate must have completed 03-06 months of training in VLSI. Candidate must have knowledge about: VLSI - Design Verification VLSI - Physical Design VLSI - Hardware VLSI - Analog Circuit Analog (Memory Design/Layout) VLSI - DFT RTL

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy. Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces. Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing. Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet. Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs. Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations. Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types. Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues. Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs. Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting. Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow. Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory. Knowledge of LogicBIST with Test point insertion, X-blocking. Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements. Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug. Ability to perform volume diagnostics on the parts to isolate and improve the patterns. Requirements Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. OR masters degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design for Test. Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows. Prior experience working on IP level and SOC level DFT projects. Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc. Worked in full chip design or complex IP delivery in the area of DFT. Experience in post silicon debug, diagnosis and yield enhancements is a plus.

Job Description: We are hiring an RTL Design Engineer with hands-on experience in FPGA-based RTL development. This role is focused on FPGA logic design and does not involve Silicon RTL or hardware testing . Key Responsibilities: RTL coding using Verilog, SystemVerilog, or VHDL Work on FPGA architecture and flow , including logic and digital design Scripting with Tcl and Python Perform synthesis and design stages using Vivado Collaborate with design teams to deliver high-quality IP blocks for FPGA

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Design. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Synthesis. Experience: 3-5 Years.

ASIC RTL DESIGN ENGINEER (4 to 10 Years) IP/SoC Design Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune/Chennai/Noida] Experience: 4 to 10 Years Openings: 6 Positions Job Description Sr RTL Design Engineer We are seeking a seasoned RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in designing state of the art solutions for automotive camera and display systems. Responsibilities Microarchitecture definition and RTL implementation ensuring optimal performance, power, area. Collaborate with software teams to define configuration requirements, verification collaterals etc. Work with verification teams on assertions, test plans, debug, coverage etc. Proficiency in Verilog/System Verilog Very google understanding of ASIC design methodologies Qualifications and Preferred Skills Graduate/Post Graduate/PhD in Electrical/Electronics 4-10 years hands-on experience in microarchitecture and RTL development Proficiency in developing micro-architecture from the design requirements, defining the H/W- S/W interface. In-depth understanding of MIPI CSI and DSI protocols Experience designing IP blocks for video and audio design Proficiency in Verilog, System Verilog Familiarity with industry-standard EDA tools and methodologies Experience with large high-speed, pipelined, and low power designs Excellent problem-solving skills and attention to detail Strong communication and collaboration skills Experience in designs complying to automotive functional safety will be a plus

This job might be for you if You enjoy solving problems. You love taking on difficult challenges and finding creative solutions. You dont know the answer but will dig until you find it. You communicate clearly. You write well. You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference. You can impress our customers with your enthusiasm to solve their issues (and solve them!) Job Description Required Solid RTL coding experience including Microarchitecture of design System Verilog and Verilog coding using provided coding styles. Understanding of SDC Understanding STA reports and how to adjust RTL accordingly. Designing for error cases and debug of IP Understanding of CDC logic Knowledge of lint rules and exceptions Design and use of block level simulations to bring up IP. Knowledge of AMBA buses and when to use them. Job Description Preferred Experienceleading small design team. C coding / Firmware skills Knowledge on common processor architectures(ARM, RiscV) FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA. Lab brings up experience, scripting. Relevant tool experience such as: Socrates, Core Consultant in additionto standard simulation tools (xcellium, vcs, etc) Emulation experience(Zebu, Palladium, etc) Board knowledge, component selection, probing, debug. JTAG debugging experience (Coresight, Lauterbach, etc). Low power design techniques Qualifications E./B.Tech. degree at minimum.

. Location: Bangalore/Kolkata Experience: 3+ years Opportunity Snapshot: We are looking to hire sharp ASIC Design Engineer with excellent communication and leadership skills. You will be part of a fast paced team responsible for delivering high-speed ASICs for large, complex systems. You will have a significant opportunity to interact with system design teams across geographies. Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team with "pay for performance" culture. Thus, you set your own limits for learning, achievements and rewards. Responsibilities: Define and architect high-performance blocks for the latest, most advanced networking ASICs Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power Collaborate with the verification team in the development of the testplan and assist in debugging test failures Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes Required Skills: 3+ years of ASIC design experience Strong Verilog RTL coding skills Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus Knowledge of high performance memory subsystems Knowledge of multi-domain clock synchronization and high-speed serial interfaces Strong problem solving and ASIC debugging skills Excellent written and verbal communications skills MSEE or BSEE is required WHERE WILL YOU DO YOUR BEST WORK

We are looking for a highly skilled Senior RTL Design Engineer with 8+ years of experience in designing complex digital IPs and SoCs. The ideal candidate should have strong RTL coding, micro-architecture, and synthesis knowledge, with a proven track record of successful tape-outs. Key Responsibilities: Develop RTL code in Verilog/SystemVerilog based on micro-architecture specifications Work on design partitioning, clock domain crossings, and low-power techniques Collaborate with verification, physical design, and DFT teams across the design cycle Perform lint, CDC, and synthesis with timing constraints Optimize design for area, performance, and power Participate in design reviews and documentation Requirements: 8+ years of RTL design experience in ASIC/SoC development Strong knowledge of digital design principles and SoC architecture Hands-on experience with RTL design tools (SpyGlass, Design Compiler, etc.) Experience with AMBA protocols (AXI, AHB, APB), FIFOs, arbiters, and bus interfaces Exposure to synthesis, STA constraints, and backend handoff Strong debugging, problem-solving, and communication skills How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future.

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers.Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLLAdditional responsibilities:logic (RTL) design, timing closure, CDC analysis etc.Understand and Design Power efficient logic.Agile project planning and execution.RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 8+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to handle the challenging problems in future technologies and designs. We are also looking for candidates with Strong C/C++background to lead our leading-edge algorithmswithin our EDA solutions to increase our design team’s productivity and chip quality and performance. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization.There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions. Individuals who are chosen to become a part of our world class development teams will be helping advance IBM’s leadership in developing the highest performing computers and changing hardware solutions. Do you want to be an IBMerCome THINK with us! Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4+ years of IT experience Strong C/C++programming skills in a Unix/Linux environment is a must. VLSI knowledge, Knowledge in front end linting tools and checkers and RTL Checkers. Great scripting skills – Perl / Python/Shell Proven problem-solving skills and the ability to work in a team environment are a must Preferred technical and professional experience RTL Lint Checkers , Front end verification flow, VLSI knowledge, VHDL/Verilog, computer architecture

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. . Required education Master's Degree Preferred education High School Diploma/GED Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design,

As a Formal verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Develop skills in IBM Formal verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 – 10 years of relevant industry experience Proven experience in Formal/Functional Verification - Demonstrated execution experience of verification of logic blocks verification. Knowledge of formal methodology, Knowledge of HDLs (Verilog, VHDL, SV), Good programming skills in python, processor core u-arch skills Exposure in developing testbench environment, debugging and triaging fails. Good communication skills and be able to work effectively in a global team environment. Drive verification coverage closure, lead verification team. Drive complex scenarios, participate in High level design discussions. Track record in leading teams. Preferred technical and professional experience Writing test plans, building random / exhaustive formal verification environment, functional and coverage analysis and debug. Good understanding of the Server System

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor core/cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

As a Silicon Design Engineer 2 at AMD, you play a crucial role in shaping the next generation of AMD products, including CPUs, GPUs, and adaptive compute engines. Your responsibilities include interfacing with large, globally distributed design teams to support complex and collaborative development efforts. You will drive automation of Synthesis, Place and Route, Logic Eqv, and Functional ECO methodologies targeting advanced technology nodes. Additionally, you will be responsible for developing and automating Synthesize, PnR, and Functional ECO for various designs at advanced technology nodes and scripting out utilities to automate different components of the implementation flow. Your role will involve collaborating closely with EDA vendors to identify innovative solutions, resolve tool/methodology issues, and enhance flow capabilities. You will contribute to the evolution of AMD's design infrastructure by improving automation, performance, and methodology robustness. Hands-on experience in Front-End Synthesis, Logical Eqv, and Conformal ECO flows is essential, along with proficiency in industry-standard tools such as DC, Fusion Compiler, FM, VCLP, ICC2, Innovus, and Conformal. Experience in PnR, STA, Formal Verification, or RTL coding domains is a plus. An automation mindset and expertise in CAD flow and methodology development on advanced process nodes are preferred. To qualify for this role, you should hold a Master's degree in Electronics Engineering and possess 3-6 years of experience in CAD flow and methodology development on advanced nodes. Proficiency in scripting languages like Python, Tcl, Perl, sed/awk is required. Strong problem-solving skills, analytical thinking, and excellent communication skills are essential. As a team player with a good work ethic, you will thrive in a collaborative environment. This position is based in Hyderabad. If you are looking to be part of a team that pushes the limits of innovation to solve the world's most important challenges, AMD could be the perfect place for you to advance your career in silicon design engineering.,

You will be joining Qualcomm India Private Limited as a Sub-System Hardware Architect specializing in ASIC design for AI within the Engineering Group > Hardware Engineering. Your primary responsibility will be to define and lead the hardware architecture for ASIC components within the Turing subsystem, ensuring they meet performance, reliability, power, and scalability requirements. You should have proven experience in designing ASIC sub-system hardware components for AI applications, strong knowledge of ASIC design tools and methodologies, and excellent problem-solving skills. Your role will involve collaborating with cross-functional teams to define hardware requirements, developing and implementing ASIC hardware architecture strategies for AI, conducting power assessment, and writing detailed hardware specifications. To qualify for this role, you should have a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with 8 to 12 years of experience in ASIC design and architecture. Additionally, you should possess expertise in micro-architecture, RTL coding, clock controller design, low power designs, and have excellent communication skills. You will be expected to provide technical guidance and mentorship to junior engineers, stay updated with the latest advancements in ASIC technology and AI applications, and ensure compliance with company policies and procedures. Qualcomm is an equal opportunity employer and is committed to providing accommodations for individuals with disabilities during the application/hiring process. If you require accommodations, you can contact Qualcomm at disability-accommodations@qualcomm.com. Please note that this email address is specifically for disability accommodations and not for updates on applications or resume inquiries.,

Experience -3+ years Experience in RTL coding using Verilog Experience on development on Xilinx MPSoC (ZCU 106/104) Hands on experience on Xilinx Vivado and Vitis, experience on Microblaze, experience on security aspects of authentication

Experience Required: Expertise and strong hands-on experience in RTL design using System Verilog or VHDL Digital system architecture, Processor subsystem architecture and block definition Experience working on complex SoCs RTL design quality analysis Lint, CDC, RDC Good understanding of digital design Synthesis, DFT and Static Timing Analysis Basic understanding of mixed-signal designs Experience with gate level simulations and debug Experience in digital verification is a plus Strong written and verbal communication skills Immediate joiners only

We are looking for experienced FPGA Verification Engineer. As a FPGA Verification Engineer, you will work for a high complexity DWDM equipment for LH/ULH applications. You will work in close collaboration with multi location cross-functional R & D teams. Our work includes everything from product concept to finished product - a process that spans over the entire development cycle. The team takes full responsibility for delivery on time with the right quality. As an FPGA Verification engineer, you will be responsible for designing verification plan, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product. Candidate should be capable of handling projects independently and strong will to drive for solutions. Education Necessary: Candidates must have a bachelors degree or higher in EE with very good academics. Roles & Responsibilities: Must have 10 years of experience in developing System Verilog UVM based test environments, developing and implementing test plans at block, sub-chip and chip levels. Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools. Exposure to UVM (or similar) verification methodologies is required. Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred. Should be conversant with technologies like, Ethernet, PCIe etc. Knowledge of telecom protocol is preferred. Structured and thorough with analytical and troubleshooting skills. Good written and oral communication skills are required. Flexible, innovative, self-driven and willing to take own initiatives. Highly motivated team player. We offer: A high pace in development of new products. Tight cooperation with other disciplines. Short product development cycles, Real results of your work, you will see how it affects our products and sales. International possibilities of development and internal advancement. Social and wellness activities and clubs. A friendly and helpful atmosphere. Highly competent and motivated colleagues.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: FPGA Design engineer Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: Strong in digital design. Strong in Xilinx Vivado IP & IPI tools till bit-generation. Knowledge of VHDL/Verilog/System Verilog. Knowledge of Validating IP/IP Example designs on Xilinx boards, debugging of failures on target boards, board bring up. Proficiency in Linux environment. Good communication skills. Basic Job Deliverable: RTL coding, IP design, Modify/update existing IP as per requirements. Qualification: Bachelors/Master’s in ECE TekWissen® Group is an equal opportunity employer supporting workforce diversity.

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be an integral part of the Circuit Technology team, focusing on DFT Methodology/Architect/RTL execution for high-speed SERDES Phys, Next-gen Memory Phys, and Die-to-Die interconnect IPs. Your responsibilities will include defining the DFX architecture for high-speed PHYs and die-to-die connectivity IP designs, RTL coding, supporting scan stitching, developing timing constraints, assisting with ATPG, and post-silicon bringup. Join a dynamic team that delivers cutting-edge IPs crucial for every SOC developed by AMD. The ideal candidate possesses strong analytical and problem-solving skills with keen attention to detail. You must demonstrate the ability to work hands-on, be a self-starter, a leader, and independently drive tasks to completion. Key Responsibilities: - Lead and define Design for Test/Debug/Yield Features specific to PHYs. - Implement DFX features into RTL using Verilog. - Comprehend DFX Architectures and micro-architectures. - Utilize JTAG (1149.1/1687/1500)/IJTAG, Scan Compression (EDT, SSH), and at-speed scan testing implementation. - Conduct gate-level simulation using Synopsys VCS and Verdi. - Perform Spyglass bringup and analysis for scan readiness/test coverage gaps. - Plan, implement, and verify MBIST. - Assist Test Engineering in planning, patterns, and debug. - Support silicon bring-up and debug. - Develop efficient DFx flows and methodology compatible with front-end and physical design flows. Preferred Experience: - Proficiency in industry-standard ATPG and DFx insertion CAD tools. - Familiarity with industry-standard DFX methodology: e.g., Streaming Scan Network (SSN), IJTAG, ICL/PDL, etc. - Knowledge of SystemVerilog and UVM. - Expertise in RTL coding for DFx logic, including lock-up latches, clock gates, and scan anchors. - Understanding of low-power design flows such as power gating, multi-Vt, and voltage scaling. - Strong grasp of high-performance, low-power design fundamentals. - Familiarity with fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware. - Exposure to post-silicon testing and tester pattern debug is advantageous. - Excellent problem-solving and debug skills across various design hierarchies. Academic Credentials: - BS/MS/PhD in EE/ECE/CE/CS with industry experience in advanced DFx techniques. Join AMD and be a part of a culture that values innovation, problem-solving, and collaboration. Together, we can advance technology and shape the future of computing.,

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

RTL DESIGN LEAD ENGINEER The ideal candidate will be required to work on both IP development and integration into SoCs catering to various markets and tech nodes. The job will involve RTL design, front-end tools flow, and SoC integration/porting-related tasks. Desired Skills and Experience- 8+ years of Experience Engineering experience with exposure to front end ASIC tool flows Should be self-driven and independent in tracking and closing tasks with respective holders. In depth knowledge of AHB and bus infrastructures like matrix and fabrics Good understanding of ARM based SoC Architecture Exposure to ARM Cortex A/M integration or support Good understanding of SoC DV methodology Good experience in Low-Power design methodology Hands-on experience with ASIC tools Lint, CDC etc System Verilog/Verilog RTL coding Power aware RTL coding/design knowledge Understanding of Clock-Structures/Scheme Good Communication Skills Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaHyderabad IndiaNoida Malaysia Singapore SwedenStockholm USATexas

VERIFICATION LEAD – IP VERIFICATION SmartSoC is looking for a smart and enterprising leader with expert knowledge in IP Verification to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking as your role will involve leading 7 to 8 projects at one time. You will be responsible for leading and managing a team, client communication, and project execution. This role will include- Lead an internal IP Verification team, executing projects for an offshore client Be responsible for Test Planning, Environment Architecture and Project Management of Multiple Projects Guide team members in verifying IP’s and delivering zero bug IP’s Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 8 – 12 years experience in Design Verification Expert Knowledge in IP Verification Very strong knowledge in multiple protocols is highly desired, AMBA protocols and at least one high speed interface Must have expert knowledge in coverage driven test planning Must have expert knowledge in architecting configurable environments Must have very strong System Verilog and UVM background Must be able to lead the team technically in all aspects, must be able to drive multiple projects Past experience leading and managing teams highly desired Excellent Communication and Presentation Skills Ability and desire to learn new methodologies, languages, protocols etc. is required Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas