41 Physical Implementation Jobs

MPU Engineering team defines and develops System on Chip, ASIC's, Digital and Analog IP's for a wide range of products, including automotive microprocessors, application processors, microcontrollers, and network processor. Responsibilities:- Lead product execution for Automotive/Consumer/Industrial ASIL-B/D SoC's Work with architects and systems engineering to define the part. Generate and analyze data to take right and cost-effective architecture decision. Work with IP, Technology, packaging partners to assess the right IP/packages and technology options for the part. Work with IP and SoC functions (front end, verification, AMS, DFT, Physical implementation) to understand and resolve inter/...

As an experienced ASIC RTL Design Engineer at MarvyLogic, you will play a crucial role in designing cutting-edge solutions that are futuristic and impactful. Your expertise in ASIC RTL Design and proficiency in Verilog/System Verilog will be key assets in this role. You will have the opportunity to work with multiple clock and power domains, integrating and validating various MIPI cores such as CSI/DSI/DPHY/CPHY/other MIPI cores. Your responsibilities will include debug tasks related to CSI/DSI, RTL design and implementation of CSI/DSI controllers, and creating block-level micro-architecture specifications. Key Responsibilities: - Utilize your 10+ years of ASIC RTL Design experience to creat...

You are seeking a talented and motivated individual to join the team at ASM Auto to work on developing cutting-edge solutions with Application-Specific Microcontrollers (MCUs) for the automotive industry. The MCUs power various vehicle functions and contribute to shaping the future of automotive technology. **Key Responsibilities:** - Define and develop microarchitecture for CPU subsystems, low-power subsystems, and Reset & Clock Management modules. - Drive SoC integration for automotive MCUs to ensure efficient and scalable designs. - Collaborate with IP teams, Systems, and Architecture teams to derive requirements and co-develop microarchitecture for IPs, subsystems, and SoC. - Work closel...

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, and more to launch cutting-edge products. You will collaborate with cross-functional teams to meet performance requirements and develop innovative solutions. **Key Responsibilities:** - 3 to 5 years of experience in static timing analysis, constraints, and other physical implementation aspects - Strong grip on STA fixing aspects for solving critical timing and clock path analysis - Experience in preparing complex ECOs for timing convergence across a wide range...

You will work as a Qualcomm Hardware Engineer at Qualcomm India Private Limited, where you will play a key role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, FPGA, and/or DSP systems to develop cutting-edge products. You will collaborate with cross-functional teams to meet performance requirements and drive innovation in the field of Hardware Engineering. **Key Responsibilities:** - Plan, design, optimize, verify, and test electronic systems - Work on circuits, mechanical systems, and various types of systems like Digital/Analog/RF/opti...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. To...

Role Overview: As a Senior RTL Design Lead at Synopsys, you will play a crucial role in leading complex ASIC digital subsystems from concept to silicon. You will be responsible for crafting subsystem architectures, developing functional specifications, implementing micro-architectures, and ensuring compliance with best RTL coding practices. Your expertise in industry-standard protocols such as PCIe, DDR, UFS, USB, and AMBA will be essential in integrating them within subsystem designs. Additionally, you will mentor junior engineers, participate in technical reviews, and drive innovation within the team. Key Responsibilities: - Lead the complete subsystem lifecycle, from requirements gatherin...

Alternate Job Titles: Senior RTL Design Lead We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and accomplished RTL design expert with a proven track record in leading complex ASIC digital subsystems from concept to silicon. Thriving on technical challenges, you find deep satisfaction in delivering first-time...

As a Senior Silicon Design Engineer at AMD, you play a crucial role in driving and improving the ability to deliver high-quality, industry-leading technologies to the market. Your contributions are instrumental in showcasing successes and facilitating continuous career development. We are seeking an adaptive and self-motivated individual to join our dynamic team. - Demonstrate a deep passion for modern, complex processor architecture, digital design, and verification. - Possess excellent communication skills and experience collaborating with engineers from different locations and time zones. - Utilize strong analytical and problem-solving skills to tackle challenges head-on. Key responsibili...

Alternate Job Titles: Principal Memory Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an accomplished and innovative engineer passionate about pushing the boundaries of embedded memory design. With a strong foundation in electrical and electronics engineering, you thrive in dynamic environments where co...

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

Role Overview: You will be responsible for ASIC RTL design with 10+ years of experience and proficiency in Verilog/System Verilog. Your role will involve working with multiple clock and power domains, integrating and validating various MIPI cores, debugging, and implementing CSI/DSI controllers. Additionally, you will be creating micro-architecture specifications, reviewing vendor IP integration guidelines, running integrity check tools, and participating in design verification and physical implementation processes. Key Responsibilities: - Possess 10+ years of ASIC RTL Design experience and proficiency in Verilog/System Verilog - Work with multiple clock and power domains - Integrate and val...

As a Qualcomm Hardware Engineer, your role involves planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. Key Responsibilities: - Utilize your 3 to 5 years of experience in static timing analysis, constraints, and other physical implementation aspects - Demonstrate a solid understanding of industry standard tools such as PT, Tempus, and familia...

Division: Artificial Intelligence Solutions Employment Status: Exempt Salary Grade: 108 Shift Requisition ID: 75816 Please be aware that if you are selected to formally interview for an internal position you will be required to notify your current manager. Please refer to the Employee Transfers Guidelines posted on Skylink. Responsibilities Digital design specification, design, analysis, and HDL (Verilog) coding Behavioral modeling of analog and mixed signal circuits Digital back-end: synthesis, physical implementation (prep for P&R), static timing, scan insertion, etc. Verification of digital sub-systems, mixed-signal sub-systems, and the entire chip using a combination of digital models/RT...

Job Details Job Description: Altera is looking for a talented and driven Silicon Design Engineering Manager to lead and inspire a multidisciplinary silicon design team. In this critical role, you will manage design engineers across multiple functional domainsincluding logic design, verification, circuit design, and physical implementationfor cutting-edge IP, subsystems, SoCs, and discrete chips. You'll be at the forefront of Altera's product innovation, driving high-quality silicon solutions that meet power, performance, area, and cost objectives. Key Responsibilities Lead and manage a team of silicon design engineers across multiple disciplines and development phases. Drive end-to-end devel...

In this role with the MPU Engineering team at NXP, you will be responsible for leading the product execution for Automotive/Consumer/Industrial ASIL-B/D SoCs. This includes working with architects and systems engineering to define the part, generating and analyzing data to make right and cost-effective architecture decisions, and collaborating with IP, Technology, and packaging partners to assess the best IP/packages and technology options. Furthermore, you will work with various SoC functions to understand and resolve inter/intra functional handoff challenges, oversee definition management, and ensure implementation compliance with requirements. Your role will also involve close collaborati...

As a Qualcomm Hardware Engineer, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems for cutting-edge products. Working closely with cross-functional teams, you will develop innovative solutions to meet performance requirements. **Key Responsibilities:** - 5 to 10 years of experience in static timing analysis, constraints, and other physical implementation aspects - Proficiency in industry standard tools PT, Tempus, GENUS, Innovus, ICC, etc. - Expertise in solving extreme critical timing bottleneck paths and p...

OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation whilst unlocking your own po...

Role Overview: You will be responsible for EMIR signoff at block and SoC level, as well as having a good understanding of IR/Power-Domain-Network signoff at SOC & block level. Your experience with RHSC tool and proficiency in Python scripting will be essential in this role. Additionally, your knowledge of Physical Implementation including Synthesis and Place & Route will be crucial. Effective communication skills, along with strong analytical and problem-solving abilities, will also be key in this position. Key Responsibilities: - Perform EMIR signoff at block and SoC level - Demonstrate a good understanding of IR/Power-Domain-Network signoff at SOC & block level - Utilize RHSC tool effectiv...